Browse Prior Art Database

Interprocessor Communications Architecture

IP.com Disclosure Number: IPCOM000108973D
Original Publication Date: 1992-Jul-01
Included in the Prior Art Database: 2005-Mar-23
Document File: 1 page(s) / 53K

Publishing Venue

IBM

Related People

Baumgartner, RS: AUTHOR [+4]

Abstract

Disclosed is a method and architecture which provides a high-speed bidirectional parallel communications path between two or more microprocessors in a multiple microprocessor system.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 62% of the total text.

Interprocessor Communications Architecture

       Disclosed is a method and architecture which provides a
high-speed bidirectional parallel communications path between two or
more microprocessors in a multiple microprocessor system.

      A common method of providing a data communications path between
multiple microprocessors in a system is by defining a bidirectional
parallel port (data bus) and several handshake port bits on each
microprocessor and interconnecting those ports.  A software protocol
implemented in each of the microprocessors supervises the writing and
reading of data to the bus ports and the assertion of sensing of the
handshake ports.

      The major drawback of this implementation is that the data bus
transaction rate is limited by the speed of execution of the software
in the microprocessors.  In the cases where data has been written to
the bus and the handshake process has been started, that process must
be completed and the bus cleared before transaction can be made by
any other microprocessor in the system.  The necessity of waiting for
a common bus to be asynchronously cleared by other microprocessors in
the system will prevent use of this architecture in applications
where the microprocessors are executing time-dependent code.

      The addition of registered transceivers with status flags
(74F550) in the data bus at the bidirectional parallel port of each
microprocessor in the system allows the data received from the bus to
b...