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Browse Prior Art Database

Data Parity Platform

IP.com Disclosure Number: IPCOM000108985D
Original Publication Date: 1992-Jul-01
Included in the Prior Art Database: 2005-Mar-23
Document File: 3 page(s) / 76K

Publishing Venue

IBM

Related People

Carey, JJ: AUTHOR [+3]

Abstract

Disclosed is a method of improving the data integrity of MICRO CHANNEL*-architected microprocessor systems by adding bidirectional parity carry through from the MICRO CHANNEL adapters to system memory. A parity bridge is used between the two systems that eliminates the expense of having to re-layout the system board. See Fig. 1.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 57% of the total text.

Data Parity Platform

       Disclosed is a method of improving the data integrity of
MICRO CHANNEL*-architected microprocessor systems by adding
bidirectional parity carry through from the MICRO CHANNEL adapters to
system memory.  A parity bridge is used between the two systems that
eliminates the expense of having to re-layout the system board.  See
Fig. 1.

      Most microprocessor systems do not support parity from the I/O
channel through to memory.  Parity is supported on the MICRO CHANNEL
and in the system memory, but there is no carry through from one
entity to the other.  Data can be read from an adapter that is
corrupted, and because of the pass through, stored in system memory
as "good" data with parity generated by the memory parity generator.

      The existing parity generator is placed on a circuit board
platform along with additional circuitry to perform the carry-through
function. A socket is placed on the system board in-place of the
parity generator module into which the platform, with its new
function, can be plugged.  See Fig. 2.  The improved parity generator
will monitor the MICRO CHANNEL DATA PARITY ENABLE signal (DPAREN) to
determine if it should check or generate parity for an adapter.  In
this way, the circuit will allow an intermix of adapters that support
parity and those that do not on the same channel simultaneously.

      The modified circuit generates parity for the following
conditions:
           1.   P...