Browse Prior Art Database

Parallel Multiple Macro Instruction Translate

IP.com Disclosure Number: IPCOM000108988D
Original Publication Date: 1992-Jul-01
Included in the Prior Art Database: 2005-Mar-23
Document File: 1 page(s) / 37K

Publishing Venue

IBM

Related People

Henry, G: AUTHOR [+3]

Abstract

Disclosed is a mechanism which decodes selective pairs of high usage CISC-based instructions and translates these complex instructions into a native RISC-based instruction. The parallel decode of high usage instructions allows for CPIs (cycles per instruction) below 1.0 to be achieved for the CISC-based instruction execution.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 90% of the total text.

Parallel Multiple Macro Instruction Translate

       Disclosed is a mechanism which decodes selective pairs of
high usage CISC-based instructions and translates these complex
instructions into a native RISC-based instruction.  The parallel
decode of high usage instructions allows for CPIs (cycles per
instruction) below 1.0 to be achieved for the CISC-based instruction
execution.

      The Intel 80386 processor instruction set architecture (ISA)
has prefix type of instructions which modify the function of the next
sequential instruction.  The prefix is one byte long.  Thus, to
decode the prefix and the instruction preceeding it in a single
clock, decode logic must be placed in two spots: at the start of the
current instruction to be decoded and one byte next to the current
instruction.  This requires two sets of decode logic.  Decoding
single-byte instructions followed by any other instruction requires
the same dual decode logic as in the prefix decode logic as stated
above.  Therefore, the decode logic and the instruction shifting
logic can be shared for both functions. Most of the single-byte CISC
instructions are of high usage.  Therefore, pairing these single-byte
instructions with any instruction is quite frequent, which, in turn,
leads to higher throughput when employing this type of
dual-instruction decoding as long as the underlying native RISC
processor can keep up with the execution of the decoded/translated
native instruction stream.

      By...