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Using a State Machine to Model the Flow of Instructions in Super Scaler RISC Processors

IP.com Disclosure Number: IPCOM000108990D
Original Publication Date: 1992-Jul-01
Included in the Prior Art Database: 2005-Mar-23
Document File: 1 page(s) / 32K

Publishing Venue

IBM

Related People

Poursepanj, AA: AUTHOR

Abstract

Modeling instructions in a performance modeling tool require keeping track of each instruction from the fetch time through the completion time. Instructions are fetched, decoded, dispatched, executed, finished, and completed as they flow through the pipeline.

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Using a State Machine to Model the Flow of Instructions in Super Scaler RISC Processors

       Modeling instructions in a performance modeling tool
require keeping track of each instruction from the fetch time through
the completion time. Instructions are fetched, decoded, dispatched,
executed, finished, and completed as they flow through the pipeline.

      Execution unit state is commonly used for modeling the
instruction flow in the pipeline.  This technique works fine for the
scaler processors, but for super-scaler processor where multiple
instructions are dispatched in each cycle, several other features,
such as interlock, out-of-order execution, register-renaming,
serialization, and in-order completion, increase the complexity of
the modeling.

      To model the super-scaler feature easier and flexible,
instructions are assigned various states such as:  FETCHED, DECODED,
DISPATCHED, FINISHED, RESOLVED (for branches only), and COMPLETED as
they flow through the pipeline.  These states are then used to
control the pipeline.

      For example, when a conditional branch instruction depends on
an instruction (A),  it cannot be RESOLVED until instruction A is
FINISHED.

      Refer to the figure.