Browse Prior Art Database

Process for Fabrication of Very Thin Epitaxial Silicon Films over Insulating Layers

IP.com Disclosure Number: IPCOM000108993D
Original Publication Date: 1992-Jul-01
Included in the Prior Art Database: 2005-Mar-23
Document File: 3 page(s) / 100K

Publishing Venue

IBM

Related People

Bronner, G: AUTHOR [+4]

Abstract

Disclosed is a process for fabrication of local silicon-on-insulator regions for high-performance device fabrication. Unlike conventional techniques, this method can provide a very thin silicon layer (100 nm or thinner if desired) over the insulator, with high degree of process control and cross-wafer uniformity. The process is as follows, with several possible variations described also.

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Process for Fabrication of Very Thin Epitaxial Silicon Films over Insulating Layers

       Disclosed is a process for fabrication of local
silicon-on-insulator regions for high-performance device fabrication.
Unlike conventional techniques, this method can provide a very thin
silicon layer (100 nm or thinner if desired) over the insulator, with
high degree of process control and cross-wafer uniformity.  The
process is as follows, with several possible variations described
also.

      The simplest embodiment is shown if Fig. 1.  Two mask levels
are used to create the structure shown in Fig. 1a, where the vertical
step "h" determines the final thickness of the silicon over the
insulator.  Afterwards, epitaxial silicon is grown selectively as
shown, with a thickness that ensures a continuous defect-free layer
over the insulator (Fig. 1b).  Then, a chemi-mechanical polish is
used to remove the excess epitaxial material.  This is a conventional
chem-mech polish process, with a very high selectivity to oxide or
nitride, so that very little of the field insulator is removed.  The
field insulator acts as a reference point for the polish, so that all
device regions end up flush with field (Fig 1c).  Since the polish
selectivity to the field insulator is very high, very little material
is removed from the field, and all the device regions end up with a
silicon layer whose thickness is determined only by the initial step
"h".

      A second embodiment is shown in Fig. 2.  Here, the field
insulator consi...