Browse Prior Art Database

Self Adapting CRT Horizontal Scan Circuit

IP.com Disclosure Number: IPCOM000109005D
Original Publication Date: 1992-Jul-01
Included in the Prior Art Database: 2005-Mar-23
Document File: 4 page(s) / 154K

Publishing Venue

IBM

Related People

Eagle, DJ: AUTHOR [+2]

Abstract

Described is a circuit function that enables a CRT display to automatically adjust the horizontal scan so that the correct data width of the displayed image is maintained irrespective of scan frequency and duty cycle over wide ranges. Performance is equal to multi-sync methods but without high costs, complexity or the need for operator intervention. A single adjustment sets widths for all modes.

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This is the abbreviated version, containing approximately 45% of the total text.

Self Adapting CRT Horizontal Scan Circuit

       Described is a circuit function that enables a CRT
display to automatically adjust the horizontal scan so that the
correct data width of the displayed image is maintained irrespective
of scan frequency and duty cycle over wide ranges.  Performance is
equal to multi-sync methods but without high costs, complexity or the
need for operator intervention.  A single adjustment sets widths for
all modes.

      CRT raster scan displays require timing information in the form
of synchronization signals which act as a reference to the scan
oscillator for stable images.  But conventional scan circuits require
parameters such as height and data phasing to be manually set using
pre-set or, for multi-sync type monitors, customer adjustments.
Different display formats use different video timing information that
can cause distorted images if the monitor is not readjusted.
Multi-sync designs make adjustments accessible to the user and, in
expensive designs, allow the settings to be recorded in memory.  This
prior art suffers from additional cost, complexity less reliability
and some inconvenience to the user.  These problems are overcome by
making use of signals which already exist in the logic hardware to
define where the video data starts and finishes in relation to the
horizontal sync pulse and provides additional data to the display for
automatic circuits to maintain constant picture size by closed loop
control.  These signals may be sent to the monitor, either separately
or multiplexed with the sync signals.

      In this article the circuit employs a video duty cycle signal
in addition to, or as a replacement for, the horizontal sync signal.
This signal is shown in Fig. 1 in relation to the video and sync
signal.  The positive going edge of this signal marks the beginning
of the video data stream and the negative going edge marks the end.
Horizontal sync is positioned somewhere in the middle but may vary
between applications in its exact position.  Using this video duty
cycle signal in place of a sync signal, allows the horizontal scan to
be synchronized by a phase-locked loop (PLL) to ensure that the video
active time is symmetrically centered within the scan period as in
Fig. 2.

      Conventional PLL circuits maintain accurate centering of the
displayed image but if the horizontal duty cycle or frequency
changes, then the width of the displayed image will vary.  The
disclosed circuit prevents this by deriving a DC control voltage
proportional to the duty cycle and comparing it with a feedback
control signal derived as a function of the peak flyback pulse
voltage which is directly porportional to the peak-to-peak current
flowing in the scan coils, (width).

      In two cases of horizontal scan waveforms shown in Fig. 3:  in
(a) the horizontal flyback time is a significant part of the total
scan period whereas in (b) it is virtually negligible.  If the same
peak-to-pea...