Browse Prior Art Database

Means to Identify Performance Limiting Delay Paths within a Chip

IP.com Disclosure Number: IPCOM000109012D
Original Publication Date: 1992-Jul-01
Included in the Prior Art Database: 2005-Mar-23
Document File: 3 page(s) / 132K

Publishing Venue

IBM

Related People

Barreh, JI: AUTHOR [+3]

Abstract

Disclosed is a method for identifying the performance-limiting delay paths within a chip. Using built-in AC tests, a binary search process has been developed to precisely identify delay paths that serve to limit the overall cycle time of the chip itself.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 48% of the total text.

Means to Identify Performance Limiting Delay Paths within a Chip

       Disclosed is a method for identifying the
performance-limiting delay paths within a chip.  Using built-in AC
tests, a binary search process has been developed to precisely
identify delay paths that serve to limit the overall cycle time of
the chip itself.

      The cycle time of a synchronous sequential machine cannot be
less than the delay of its longest internal (latch-to-latch) path.
An important performance screening method for VLSI logic circuits has
been the use of built-in AC self-tests to determine the cycle time at
which a VLSI chip will fail.  In order to generate a failure,
built-in AC tests are performed at successively greater clocking
frequencies (shorter cycle times) until a failure is observed.  This
failure is the result of delays in internal (latch-to-latch) logic
circuit paths which are too long to resolve correctly at the failing
cycle time.  The AC test procedure entails the application of a large
number (usually a million or more) test patterns, but produces a
single result:  a binary string (signature) which characterizes the
complete set of states which have occurred in the machine during the
test.  If the signature obtained at the test clock frequency matches
that of the good machine (actually the same hardware operated at a
clock cycle time which is greater than the longest internal path
delay), then the result of the test is considered to be a success.
If the signatures fail to match, this indicates that at least one of
the patterns generated during the test activated a circuit network
with a path delay in excess of the test cycle time.  However, there
is no indication of which pattern(s) caused the failure or of which
logic circuit path(s) failed to resolve correctly.

      The invention disclosed here is a procedure for determining the
specific test pattern for which an incorrect machine state first
occurred during AC self-test, and for identifying the failing logic
circuit path(s).  The procedure is applied after determining the
lowest "test" frequency at which the AC test fails.  The first
failing test pattern is identified by performing a binary search
through the fixed sequence of patterns generated by the AC test,
using a good-machine, bad-machine approach.  That is, at each
iteration of the search, a "good" signature is obtained by running AC
self-tests at the "good" (slow) clock frequency for some number of
test patterns (P).  A corresponding signature is obtained by running
the AC tests for the same number of patterns at the "test" clock
frequency.  If the two signatures are different (as they must be in
the first iteration of the search, when P equals the total number of
patterns in the complete AC test), a smaller value of P is selected
for the next iteration.  If the two signatures are identical, a
larger value of P is selected.  If a binary search algorithm is used
for the selection of P, the maximum n...