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Switch Chip for a Multiprocessing System

IP.com Disclosure Number: IPCOM000109014D
Original Publication Date: 1992-Jul-01
Included in the Prior Art Database: 2005-Mar-23
Document File: 4 page(s) / 167K

Publishing Venue

IBM

Related People

Jaber, TK: AUTHOR

Abstract

In multiprocessing systems, memory and I/O space data must be accessible to any processing element (PE) at any given time, and any processing element must be able to access memory or I/O space. This multiprocessing architectural requirement necessitates the existence of a switch function between the PE units and the storage elements. This article describes a modular chip design that would allow for the implementation of such a switch function.

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This is the abbreviated version, containing approximately 51% of the total text.

Switch Chip for a Multiprocessing System

       In multiprocessing systems, memory and I/O space data
must be accessible to any processing element (PE) at any given time,
and any processing element must be able to access memory or I/O
space.  This multiprocessing architectural requirement necessitates
the existence of a switch function between the PE units and the
storage elements.  This article describes a modular chip design that
would allow for the implementation of such a switch function.

      The chip dataflow is shown in Fig. 1.  The chip interfaces
primarily with the PE units and the memory units.  An I/O data buffer
exists to account for the difference in bandwidth between the I/O bus
and the memory bus on one side and the PE data bandwidth on the
other, CPU, side.  In this particular case, the system consists of 4
processor elements and an equal number of memory banks.  During
memory store operations, the PE data goes through a network that
consists of 4 one-word-wide registers that are preceded by 6 (6 to 1)
multiplexers that allow for selecting and connecting any processor
element to any memory bank during memory store operations.  The store
switch also allows for IO buffered data to be stored in memory.  IO
data is first buffered up off the IO buses in IO write buffers and
then a path from these buffers to the memory banks is established
through the store switch.

      The control signals that control this network, as well as, the
chip CPU side receivers and memory side drivers originate from a
storage control unit chip (SCU) that oversees data traffic to and
from memory and is also responsible for guaranteeing cache coherency
among the various processing units and between PEs and memory.  Note
that the data movement between any PE and any of the memory banks
should not be delayed by more than one cycle time during memory store
operations by virtue of the store data going through the switch chip.
This performance requirement also necessitates that data flows from
the PEs to the switch logic in less than one cycle time and from the
switch logic to memory, also, in less than one cycle time.

      The load switch logic includes 10 one-word-wide registers.
Each of these registers is preceded by a 5:1 (one-word-wide)
multiplexer.  During memory load operations, load data must not be
delayed for longer than one cycle time by virtue of its going through
the switch chip in destination to any of the processing elements. The
load switch logic allows load data to originate from any of the
memory banks and routes data to any of the proce...