Browse Prior Art Database

High Performance, Soft Error Immune Bipolar Memory Cell

IP.com Disclosure Number: IPCOM000109039D
Original Publication Date: 1992-May-01
Included in the Prior Art Database: 2005-Mar-23
Document File: 1 page(s) / 37K

Publishing Venue

IBM

Related People

Jordy, GJ: AUTHOR [+2]

Abstract

In high performance bipolar memory cell design, it becomes increasing sensitive to high energy particle noise, since high density memory cell collected most charge in the subcollector region as the transistor operated in forward mode. Although saturated cells have been designed, it has high soft error rate due to smaller capacitance in the critical node on the advanced transistor to achieve high performance.

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High Performance, Soft Error Immune Bipolar Memory Cell

      In high performance bipolar memory cell design, it becomes
increasing sensitive to high energy particle noise, since high
density memory cell collected most charge in the subcollector region
as the transistor operated in forward mode.  Although saturated cells
have been designed, it has high soft error rate due to smaller
capacitance in the critical node on the advanced transistor to
achieve high performance.

      New bipolar memory cell, such as shown in FIG. 1, by using PNP
device as load and NPN diode as read-write devices, is designed to
achieve soft error immunity.  The cross coupled devices are operated
in inverse mode.  Thus, the charge collected from energetic particle
noise in the critical node is minimized.  Its read access time is the
same as conventional saturated cell and provides faster write time.
In the layout to achieve high density, the load device and
cross-coupled device is merged together.  The subcollector contact to
node DL is only needed about every 8 cells.  It is a stable cell and
less sensitive to leakage current.  The resistor in the cell can be
polysilicon resistor and also integrated with half cell.

      Disclosed anonymously.