Browse Prior Art Database

Overlay Verification Reticle for Semiconductor Mask Sets

IP.com Disclosure Number: IPCOM000109048D
Original Publication Date: 1992-May-01
Included in the Prior Art Database: 2005-Mar-23
Document File: 1 page(s) / 71K

Publishing Venue

IBM

Related People

Jacobsen, LB: AUTHOR [+4]

Abstract

A method for determining the source of layer-to-layer registration (overlay) errors on semiconductor wafers is disclosed. Product wafers with questionable registration can be exposed on a "Star Mask" with multiple vernier sites. Registration values obtained determine whether the problem exists with the reticle placement or with a prior level or stepping tool.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Overlay Verification Reticle for Semiconductor Mask Sets

      A method for determining the source of layer-to-layer
registration (overlay) errors on semiconductor wafers is disclosed.
Product wafers with questionable registration can be exposed on a
"Star Mask" with multiple vernier sites. Registration values obtained
determine whether the problem exists with the reticle placement or
with a prior level or stepping tool.

      A multiple site test reticle with verniers in a "Star" array
was designed. "Star Mask" A contains all lower vernier targets and
"Star Mask" B has all upper vernier targets. Additional vernier sites
were added consistent with standard GCA overlay calibration
techniques for increased accuracy.

      "Star Mask" A can be exposed on product wafers and vernier
sites read to determine mask build problems such as misaligned data
or pellicles. "Star Mask" B reticle is exposed on A level artifact
wafer to determine potential stepper errors.  "Star Mask" B reticle
exposed on a product wafer will determine if registration errors are
from a prior level.

      Determining the source of layer-to-layer registration error
(overlay) on semiconductor wafers is a problem. Registration errors
may be caused by the lithography tool used to expose the masking
layers, the mask itself, or the underlying layers on the wafer.

      To address the problem stated above, a test mask was designed.
This mask included appropriate stepper alignment targets, ve...