Browse Prior Art Database

Video Frame Buffer with Increased Performance Capability

IP.com Disclosure Number: IPCOM000109062D
Original Publication Date: 1992-Jul-01
Included in the Prior Art Database: 2005-Mar-23
Document File: 6 page(s) / 242K

Publishing Venue

IBM

Related People

Bischoff, G: AUTHOR [+3]

Abstract

The memory organization of the frame buffer is the limiting factor to the update performance of frame buffered raster scan displays. The memory organization determines how many and which pixels can be accessed in a single memory cycle, and hence limits the number of pixels that can be updated in parallel by the update hardware. High performance displays frequently allow parallel update to the frame buffer, effectively resulting in a lower memory cycle time per pixel.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 30% of the total text.

Video Frame Buffer with Increased Performance Capability

       The memory organization of the frame buffer is the
limiting factor to the update performance of frame buffered raster
scan displays.  The memory organization determines how many and which
pixels can be accessed in a single memory cycle, and hence limits the
number of pixels that can be updated in parallel by the update
hardware.  High performance displays frequently allow parallel update
to the frame buffer, effectively resulting in a lower memory cycle
time per pixel.

      The parallel update required is clearly dependent upon the size
and shape of the objects being drawn into the frame buffer as well as
the memory available and the memory technology.  There are several
frame buffer organizations that allow the parallel access of several
pixels if they are in a horizontal line or if they are in an
arbitrary square.

      The implementation of memory organizations determines the cost
and complexity of frame buffered systems and their associated update
hardware.  The memory organizations and their implementations hence
become critical in determining the cost and functionality of frame
buffered displays.  Because of the nature of memory chips, the
complexity of the frame buffer organization is uniquely determined by
the number of memory chips and the number of unique signal wires
connected to them.  These wires are the address wires (usually
multiplexed into Row Address and Column Address signals), data wires,
and the control signals (Row Address Strobes, Column Address Strobes,
and the Write Enables).

      A frame buffer organization which allows the access of 16
arbitrarily aligned horizontal pixels is described in (1).  This is
achieved by using 16 memory chips (64 Kilobits each) to realize a 1K
by 1K frame buffer.  The ability to access an arbitrarily aligned
word is achieved by strobing different column addresses to different
chips depending upon the left boundary of the desired word.  The
implementation uses one address bus, but 16 column address strobe
wires.  The first address is driven and the appropriate chips
strobed, followed by the second address and the strobe of the rest of
the chips.  This implementation requires a longer memory cycle but
only 8 address signals.

      To optimize the access for different operations, the access to
an 8 by 8 array of pixels that could be arbitrarily aligned was
implemented in (2).  The 8 by 8 display had eight sets of address
buses (8 wires each) which could deliver different addresses to
different columns of the 8 by 8 array of memory chips.  The memory
organization used provided different row addresses by using the same
address wires and providing different column strobes, and provided
different column addresses by driving different addresses on
different columns.

      Another complication is a number of data signals.  In the 8 by
8 display example, an 8-bit-per-pixel frame buffer woul...