Browse Prior Art Database

BiCMOS Isolation Technology Using Epitaxial Lateral Overgrowth and Preferential Polishing

IP.com Disclosure Number: IPCOM000109082D
Original Publication Date: 1992-Jul-01
Included in the Prior Art Database: 2005-Mar-23
Document File: 2 page(s) / 121K

Publishing Venue

IBM

Related People

Burghartz, JN: AUTHOR [+3]

Abstract

Disclosed is a BiCMOS isolation structure for low-power applications with a CMOS device on silicon-on-insulator (SOI), and a bipolar transistor featuring very low device parasitics. The fabrication technology involves selective epitaxial refill and overgrowth combined with preferential polishing.

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BiCMOS Isolation Technology Using Epitaxial Lateral Overgrowth and Preferential Polishing

       Disclosed is a BiCMOS isolation structure for low-power
applications with a CMOS device on silicon-on-insulator (SOI), and a
bipolar transistor featuring very low device parasitics.  The
fabrication technology  involves selective epitaxial refill and
overgrowth combined with preferential polishing.

      The isolation structure is built of a technology module which
is applied twice to fabricate a vertical bipolar transistor and a
CMOS device on SOI at the same level with the field dielectric (Fig.
1).  The fabrication step for the module is as follows: Two
dielectric films (1,2 in Fig. 1) are deposited on a p-type silicon
substrate.  A shallow groove is etched into film 2, followed by
etching a concentric, narrower groove into film 1.  Selective
epitaxial growth 3 is carried out to refill the narrow groove and to
overgrow laterally into the shallow groove to form SOI 4 adjacent to
the epi-seed region.  Since the overgrowth fills the shallow groove
only partly, polysilicon is deposited to complete the refill.  Both
the selective epi extending vertically above the field dielectric
level as well as the polysilicon outside of the shallow groove are
removed next by preferential polishing which makes the epi and poly
level with the field dielectric.  After polishing, the fabrication
process for the first module is completed (Module I in Fig. 1).
Next, the module is applied a second time.  While the fabrication
process flow is very similar, the dielectric films 5,6 are thinner,
and the epi overgrowth is used now to form SOI regions on the CMOS
side 7.  The SOI is isolated from...