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Vertical Source/ Drain Contacts for SOI Based MOSFETs

IP.com Disclosure Number: IPCOM000109093D
Original Publication Date: 1992-Jul-01
Included in the Prior Art Database: 2005-Mar-23
Document File: 2 page(s) / 69K

Publishing Venue

IBM

Related People

Hovel, HJ: AUTHOR [+3]

Abstract

The parasitic series resistance of MOSFETs does not scale with device scaling. The resistance consists of several components, such as sheet resistance of the channel, sidewall (n region) and n+ regions, contact resistance, etc. However, the effective resistance at the channel/ drain edge is difficult to determine due to the current crowding at the edge. Even though some of the resistance components can be well characterized, the resistance due to current crowding in the vicinity of a channel edge is hard to characterize. This is because current crowding depends on a variety of parameters including material properties of Si (such as those that govern hot electron behavior), electric fields, p-n junction characteristics (including doping gradient), etc.

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Vertical Source/ Drain Contacts for SOI Based MOSFETs

       The parasitic series resistance of MOSFETs does not scale
with device scaling.  The resistance consists of several components,
such as sheet resistance of the channel, sidewall (n region) and n+
regions, contact resistance, etc.  However, the effective resistance
at the channel/ drain edge is difficult to determine due to the
current crowding at the edge.  Even though some of the resistance
components can be well characterized, the resistance due to current
crowding in the vicinity of a channel edge is hard to characterize.
This is because current crowding depends on a variety of parameters
including material properties of Si (such as those that govern hot
electron behavior), electric fields, p-n junction characteristics
(including doping gradient), etc., at the channel edge, and these are
difficult to determine during device operation.

      In this article a new process is described to fabricate
vertical source/drain contacts.  This scheme allows an increased
contact surface area as well as controlled doping under the sidewall
region.  The process requires an SOI substrate, n or p-dopant
diffusion and low temperature selective Si epitaxy.

      Fig. 1e shows a schematic view of the proposed Si-MOSFET.
Figs.  1a - 1e illustrate the process sequence to realize the device.
Basically, after gate patterning and formation of sidewalls, it is
proposed that the Si on both sides of sidewalls be remov...