Browse Prior Art Database

Memory Evaluation

IP.com Disclosure Number: IPCOM000109106D
Original Publication Date: 1992-Jul-01
Included in the Prior Art Database: 2005-Mar-23
Document File: 1 page(s) / 49K

Publishing Venue

IBM

Related People

Shen, WW: AUTHOR [+2]

Abstract

Disclosed is an apparatus for both the characterization and self-test of a computer memory in a high utilization environment. The results are achieved with a minimum of software and hardware support. The memory controller receives a signal commanding it to generate memory fetch requests during the time intervals the memory is not busy with normal activities. This creates near 100% utilization of the memory and its associated controls and data paths. Normal activities, therefore, would find a high degree of contention for memory resources. The signal commanding the controller to generate the internal requests is a steady state type or a cyclical type whose period and duty cycle can be controlled through programming variables.

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Memory Evaluation

      Disclosed is an apparatus for both the characterization and
self-test of a computer memory in a high utilization environment.
The results are achieved with a minimum of software and hardware
support.
The memory controller receives a signal commanding it to generate
memory fetch requests during the time intervals the memory is not
busy with normal activities.  This creates near 100% utilization of
the memory and its associated controls and data paths.  Normal
activities, therefore, would find a high degree of contention for
memory resources.
The signal commanding the controller to generate the internal
requests is a steady state type or a cyclical type whose period and
duty cycle can be controlled through programming variables.
The data obtained as a result of the internally generated fetch
requests is not used but can be monitored for errors.  Likewise, the
intermixed normal activities can be monitored for data and control
errors.
The location accessed within the memory for the internally generated
requests is the last location accessed by normal activities.  As
normal activities use the memory, the internally generated accesses
move to different locations within the memory.
The apparatus provides a mechanism for one of the normal activities
to continually make requests to random memory locations so that the
internally generated accesses will also continually move to the same
random locations.

      Anonymous.