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Prevention of Salicide Bridging using Dry Etching

IP.com Disclosure Number: IPCOM000109162D
Original Publication Date: 1992-Jul-01
Included in the Prior Art Database: 2005-Mar-23
Document File: 1 page(s) / 56K

Publishing Venue

IBM

Related People

Polcari, MR: AUTHOR [+2]

Abstract

A technique is described whereby salicide bridging, as can occur in semiconductor technologies which use salicide processing, is prevented by using dry etching. (Image Omitted)

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Prevention of Salicide Bridging using Dry Etching

      A technique is described whereby salicide bridging, as can
occur in semiconductor technologies which use salicide processing, is
prevented by using dry etching.

                            (Image Omitted)

      Salicide processing, the forming of a self-aligned silicide on
both the source/drain (S/D) and gate regions of field-effect
transistors (FETs), has become an important part of MOS technologies,
particularly CMOS.

      The most commonly used metal, Ti, suffers from the disadvantage
of bridging being caused during fabrication.  Following the
disposition and initial reaction of Ti with the silicon, a
preferential wet etch is used to remove the residual Ti over the
oxide regions.  This is followed by a second thermal reaction which
causes the full formation of the TiSi2 .  Although this process
provides an isolated gate and S/D region, an apparent thin conducting
layer remains on the dielectric spacer causing a leakage path between
the gate and the S/D.  The figure illustrates this type of structure.

      The concept described herein utilizes a dry etch process to
remove the thin conducting layer and a few hundred Ao of the
sidewall.  This causes the gate and the S/D regions to be
electrically isolated.  The dry etch process should have sufficient
selectivity to the TiSi2, such that an insignificant amount of
material is removed, while eliminating the bridging ar...