Browse Prior Art Database

Hardware Assist to Execute the STAM ESA/390 Instruction

IP.com Disclosure Number: IPCOM000109189D
Original Publication Date: 1992-Aug-01
Included in the Prior Art Database: 2005-Mar-23
Document File: 2 page(s) / 101K

Publishing Venue

IBM

Related People

Lei, CI: AUTHOR

Abstract

An algorithm is disclosed for executing the Store Access Multiple (STAM) instruction without slowing down the process to resolve Segment Table Designator (STD) miss.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Hardware Assist to Execute the STAM ESA/390 Instruction

       An algorithm is disclosed for executing the Store Access
Multiple (STAM) instruction without slowing down the process to
resolve Segment Table Designator (STD) miss.

      For the ESA/390* architecture, a set of sixteen 32-bit
registers, known as the access registers, are implemented.  The
content of the access registers is indirectly related with the
address spaces addressable by the program.  The translation process
to relate the access register content to the STD of the address space
is called access register translation (ART).

      Hardware must have the capability to deal with virtual
addresses from different address spaces concurrently.  Virtual to
absolute address translations from different address spaces can
reside in the Translation Look-aside Buffer (TLB) at the same time.
Therefore, a tag of the address space must be included in the TLB for
each virtual to absolute translation.  The tag used is the segment
table origin (STO) of the address space.  Thus, a storage access must
match not only with the virtual entry in the TLB, but also with the
STO associated.

      Storage operations point to access registers through the B or R
field of the 390 instruction, and these indirectly relate to the
address spaces.  Due to the fact that ART is a complex process, the
STO resulting from ART is saved in a special array called the ART
Look-aside Buffer (ALB).  The STO is then transferred from the ALB
array to the STD array.  Each time an access register is updated, ART
must be invoked to determine the associated address space.  However,
if the content of the updated access register is the same as another
access register, then ART may have already been performed on the
other access register, and the corresponding address space can be
found in the ALB array.  Getting a translation from the ALB array is
much faster than from ART.

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