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Method for improving the performance of CRC generation algorithms using gather-XOR instructions

IP.com Disclosure Number: IPCOM000109203D
Publication Date: 2005-Mar-23
Document File: 4 page(s) / 82K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for improving the performance of cyclic redundancy code (CRC) generation algorithms using gather exclusive OR (XOR) instructions. Benefits include improved functionality, improved performance, and improved cost effectiveness.

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Method for improving the performance of CRC generation algorithms using gather-XOR instructions

Disclosed is a method for improving the performance of cyclic redundancy code (CRC) generation algorithms using gather exclusive OR (XOR) instructions. Benefits include improved functionality, improved performance, and improved cost effectiveness.

Background

              Internet and datacenter applications require reliable and secure transactions at gigabit-per-second (Gbps) rates. To detect changes of content in transit, a number of server protocols support sophisticated data integrity checks, using the CRC32C or other polynomials. Conventional software-based CRC generation algorithms are computation-intensive and fail to meet the requirement of high-speed (such as several Gbps) packet processing by Internet servers.

              Gather memory instructions have been proposed as part of several processors but not widely accepted.

              Conventional               software-based CRC algorithms are table driven and operate at moderate speeds.

General description

              The disclosed method uses multiple tables for memory accesses. Additionally, an exclusive-OR (XOR) operation is required when memory accesses are complete for the content of the destination register to be determined.

      The disclosed method can be parallelized in a many-core environment. The method can be accelerated using architectural extensions.

              The key elements of the disclosed method include:

•             A flavor of GXOR<number of bits> instructions which are supported in environments where the word size may vary:

      Example 1: A GXOR32 instruction for use in 32-bit operating environments

      Example 2: A GXOR64 instruction for use in 64-bit operating environments

•             Source operand sliced into a variable number of slices of a variable number of bits each, for    accessing a variable number of tables. The number of tables should be equal to the number of slices. The number of entries in each table should be equal to 2 to a power equal to the number of bits contained in each slice.

              Example 1: A 32 bit word is sliced into 4 slices of 8 bits each. Each slice is used for accessing one of 4 tables, where each table contains 256 32-bit entries.

      Example 2: A 64 bit word is sliced into 8 slices of 8 bits each. Each slice is used for  accessing one of 8 tables, where each table contains 256 32-bit entries.

•             XOR operation performed on the tables

•             Result placed in the destination register

Advantages

              The disclosed method provides advantages, including:
•             Improved functionality due to providing a number gather-exclusive-OR instructions, such as GXOR32 and GXOR64

•             Improved functionality due to reducing the number of cores required for CRC generation

•             Improved performance due to accelerating table-driven software-based CRC generation algorithms that can be...