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Formation of dummy solder patterns as an alpha partice barrier for integrated circuits

IP.com Disclosure Number: IPCOM000109207D
Original Publication Date: 2005-Mar-23
Included in the Prior Art Database: 2005-Mar-23
Document File: 2 page(s) / 29K

Publishing Venue



Disclosed is a structure to reduce SER (soft error rate) in high performance ICs (integrated circuits). For newer CMOS technologies, SER (soft error rate) caused by alpha radiation is an increasing concern. It has been found that one of the main causes of alpha particle is the ceramic substrate used for packaging these devices. The disclosure proposes to use low-alpha solder deposited during wafer fabrication as an effective barrier for these alpha particles.

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Formation of dummy solder patterns as an alpha partice barrier for integrated circuits

It has been observed that latches of the type used in advanced CMOS technology have become sensitive to alpha particle induced single event upsets (SEU). Single event upsets (SEU) are transient events that change the state of a charge-holding node of a circuit. SEUs may lead to machine state errors. These can crash the system, resulting in a UIRA (unplanned incident repair action) and can produce silent errors which may compromise data integrity. This increased latch upset sensitivity raises concern for the reliability and data integrity of forthcoming computer systems. Devices built in advanced silicon technology are increasingly susceptible to both noise-induced and transient particle-induced SEUs because of decreasing feature size, increasing density, and decreasing voltage. The alpha particle sensitivity of latches in logic paths to single event upsets (SEU) has increased with 0.13 um process technology, requiring latch and register files to be considered in the overall soft error rate (SER). SER from combinatorial logic is expected to become a factor in the 45 nm process node.

The disclosed structure is a grid of solder structures that are placed between C4 balls. It has been shown that low-alpha solder is an effective barrier against alpha particles such as can be emitted by the ceramic substrate. Such solder structures can be deposited during the normal FBEOL (far back e...