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Rate Adaptation and Multiplexing Format for High Performance Scanning Function

IP.com Disclosure Number: IPCOM000109250D
Original Publication Date: 1992-Aug-01
Included in the Prior Art Database: 2005-Mar-23
Document File: 3 page(s) / 111K

Publishing Venue

IBM

Related People

Badaoui, M: AUTHOR [+5]

Abstract

The ECMA standard performs the multiplexing function of 8 users at 4800 bps on the same 64 Kbps slot, each user having its bit stream on one dedicated bit of the slot. This method requires a scanner working bit by bit, 8-bit scanning functions must be done in one 64 Kbps slot time duration. The disclosed format is based on a slot multiplex, each 4800 bps user having slots, in which the 8 bits belong to this same user. This allows the scanner to work byte per byte 8 time slower. In addition it can support 8 times more users (with a given technology) versus ECMA standard format. PROPOSED FORMAT

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Rate Adaptation and Multiplexing Format for High Performance Scanning Function

       The ECMA standard performs the multiplexing function of 8
users at 4800 bps on the same 64 Kbps slot, each user having its bit
stream on one dedicated bit of the slot.  This method requires a
scanner working bit by bit, 8-bit scanning functions must be done in
one 64 Kbps slot time duration.  The disclosed format is based on a
slot multiplex, each 4800 bps user having slots, in which the 8 bits
belong to this same user.  This allows the scanner to work byte per
byte 8 time slower.  In addition it can support 8 times more users
(with a given technology) versus ECMA standard format.
PROPOSED FORMAT

      Three consecutive slots, two Data Slots and one Control Slot,
are dedicated to the same user, as shown below:
     0    1    2    3    4    5    6    7
     X    X    X    X    X    X    X    0     Data Slot
                                                        User 0
     X    X    X    X    X    X    X    1     Data Slot
     A    A'   Xr  I/P   E    E    E    1     Control Slot

      The format is based on the slot format described in the U.S.
Patent 4,760,573.
     1. A variable delimiter allows any type of clock, any value even
variable.
     2. The use of A,A' variable delimiter and DCE bits in the
Control slot allows network independent clock and DCE interface
management up to 72 Kbps with one Data Control couple, and up to
2.048 Mbps with N (Data Control slot couples).
      3. The bit 7 is used for frame delimiter.
         a. 0 in the first slot of the first user.
         b. 1 in other slots.
      4. The Xr (Transmit Request) bit is used as defined in the
above referenced patent except than when raised the Line Interface
Card which controls the described multiplex format and standard
interfaces such as RS232 C, X21, V35 .... requires a slot burst of
(up to) 16 valid bits.
      5. I/P bit. Working alternatively I then P are given on the
same bit.
         a. I carries internal Line Interface Card registers
information.
         b. P carries the Parity of the 6 slots (preceding burst and
current burst).
      6. E bits carries Data Communication Equipment information.
      7. The bits 0 to 6 of the 2 Data Slots, with A A' of
the Control Slot provi...