Browse Prior Art Database

Synchronous Processor Bus Controller

IP.com Disclosure Number: IPCOM000109255D
Original Publication Date: 1992-Aug-01
Included in the Prior Art Database: 2005-Mar-23
Document File: 2 page(s) / 79K

Publishing Venue

IBM

Related People

Banks, WP: AUTHOR [+6]

Abstract

Disclosed is an architecture which provides multiple attachments of different Microprocessor Bus Controller (PBC) to common microprocessor cores. The architecture provides a menu of processor core offerings and PBC offerings providing for a mix and match of each. Both core and PBC share common interfaces to provide this capability.

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This is the abbreviated version, containing approximately 63% of the total text.

Synchronous Processor Bus Controller

       Disclosed is an architecture which provides multiple
attachments of different Microprocessor Bus Controller (PBC) to
common microprocessor cores.  The architecture provides a menu of
processor core offerings and PBC offerings providing for a mix and
match of each.  Both core and PBC share common interfaces to provide
this capability.

      Currently, there is a close association between the
microprocessor core and the PBC.  The PBC often determines the
choices in peripheral logic chips and the amount of glue logic
required to provide attachment of a particular peripheral chip.
Often, inefficient trade-offs are made since processor selection is
based on the core architecture and performance of the processor.  If
a peripheral device, such as a DMA Controller, were needed, but none
was available for the particular PC, then one had to be either
designed from scratch or an existing one would have to be attached
via glue logic.  This often causes "reinvention of the wheel" which
translates to increased development expense.

      With the microprocessor core independent of the PBC, one can
choose the core based on the richness of the instruction set or
robustness of the interrupt mechanism while selecting a PBC which
provides attachment to many off the shelf peripheral chips.  This
enhances choices of function while minimizing development expense.

      This architecture, with reference to the figure, was proven...