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Chip Alignment Check Circuit and Test Method

IP.com Disclosure Number: IPCOM000109260D
Original Publication Date: 1992-Aug-01
Included in the Prior Art Database: 2005-Mar-23
Document File: 3 page(s) / 93K

Publishing Venue

IBM

Related People

Hinrichsmeyer, K: AUTHOR [+3]

Abstract

This article describes a test method by which incorrectly placed and rotated chips are detected before they are soldered to a carrier.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 79% of the total text.

Chip Alignment Check Circuit and Test Method

       This article describes a test method by which incorrectly
placed and rotated chips are detected before they are soldered to a
carrier.

      For this purpose, chip pads (orientation, unoccupied or
additional pads) are provided which are connected to a predetermined
potential or short-circuited.

      By means of test probes fixed to a ram, a contact resistance or
pressure is measured for correctly placed chips, which is used to
control the further production process.  Placement and measurement
are effected in the same step and thus do not require additional
equipment.  Time losses during packaging are avoided.

      The minimum solution consists of an orientation pad which is
connected to ground on the chip.  On the chip carrier, this pad is
linked to a test pad which is accessible by a test probe even after
chip placement.  In this case, the chip footprint does not have to be
changed (Figs. 1, 2, 3A, 3B).  In a special embodiment, more than one
pad, i.e., at least two pads are short-circuited on one, two or four
corners of the chip (Fig. 4).  On the chip carrier, the pads are
provided with lines terminating at the test pad.  In this case, the
footprint has to be changed slightly.

      Further alternatives include a pick-up and placement head with
an orientation test system, which is permanently fixed thereto.  The
check indicator may be an electrical, optical or acoustic one.  Pads
and c...