Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

New Interface Between HDC and Host Interface LSI

IP.com Disclosure Number: IPCOM000109264D
Original Publication Date: 1992-Aug-01
Included in the Prior Art Database: 2005-Mar-23
Document File: 3 page(s) / 84K

Publishing Venue

IBM

Related People

Kigami, Y: AUTHOR [+4]

Abstract

Disclosed is a technique to build intelligent communication between HDC (Hard Disk Controller) and HI (Host Interface) LSI on a hard disk sub-system. By applying this interface, not only data, but commands and parameters, can be transferred in between HDC and HI.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

New Interface Between HDC and Host Interface LSI

       Disclosed is a technique to build intelligent
communication between HDC (Hard Disk Controller) and HI (Host
Interface) LSI on a hard disk sub-system.  By applying this
interface, not only data, but commands and parameters, can be
transferred in between HDC and HI.

      Fig. 1 shows the hardware diagram of this technique.  Two extra
signals, -HIRRD and -HIRWT, are added on the current configuration.

      There are basically two operation modes in this new interface.
One is traditional DMA data transfer (MODE 1) and another is command
& parameter transfer (MODE 2).  When DMA data transfer has completed,
this mode is switched to MODE 2 automatically.

      In general Disk Subsystem, HDC has more intelligence compared
to HI and the main control of MODE2 transfer should be done by HDC.
So this interface adds capability to access (read & write) the
register sets in HI.  As shown in MODE2 in Fig. 1, 16-bit data bus
was separated into 8-bit address and 8-bit data.

      To read data on HI register, -HIRRD signal and register
addresses are activated by HDC and HI outputs data on register
through 8-bit data.  Then, HDC can get register data at the rising
edge of -HIRRD signal, as shown in Fig. 2.

      To write data to HI register, -HIRWT signal, register addresses
and data are activated by HDC.  Then, HI can store the data at the
rising edge of -HIRWT signal, as shown in Fig. 3.