Browse Prior Art Database

Dimple Short Repair

IP.com Disclosure Number: IPCOM000109296D
Original Publication Date: 1992-Aug-01
Included in the Prior Art Database: 2005-Mar-23
Document File: 3 page(s) / 156K

Publishing Venue

IBM

Related People

Koblinger, O: AUTHOR

Abstract

This article describes a dimple short repair (DSR) process.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Dimple Short Repair

       This article describes a dimple short repair (DSR)
process.

      A standard process for filling steep studs in insulators
consists of blanket depositing metal on the insulator and in the
studs previously produced therein.  Excess metal on the insulator is
removed by standard processes.  Surface irregularities of the
insulator, such as grooves or holes, also known as dimples, are
filled in the metal deposition step.  In the subsequent polishing
step of the substrate, these dimples, which are located on a
different plane, are protected by the metal covering them in the form
of a "puddle".

      Such metal puddles may bridge the studs.  They may also
interconnect subsequently deposited metal lines, in addition to
linking, i.e., electrically short-circuiting, these lines to a stud
(residual metal).  Owing to the size of the puddles, laser short
repair is unsuitable.  If, on the other hand, for eliminating such
short circuits, too much of the insulator is removed by polishing,
electromagnetic decoupling between the metal layers and insulating
properties will no longer be guaranteed.

      A general disadvantage of known repair processes is that
dimples have to be localized by inspection before any repair is
possible.  At that stage of processing, it is difficult to determine
which metal residues may lead to shorts between adjacent metal lines
or studs at a later date.

      The decisive feature of the inventive concept is to use the
'design' of the follow-on metallization to locate short-circuits.
For this purpose, metal lands in the upper wiring level are simulated
by resist lands, i.e., a negative resist is applied to the stud layer
(Fig. 1A) and exposed, using the same wiring mask (full metal mask)
as in the subsequent metallization step (Fig. 1B).  This is followed
by a metal etch (preferably a wet chemical subetch or RIE) step until
the amount of metal removed by etching corresponds to the nominal
insulator thickness.  In other words, undesired metal connections
between lines or studs are reliably etched open down to the base of
the insulator or the underlying metallization, while the original
state of the insulator surface remains unaffected (Fig. 1C).  Then,
the metallization is applied as usual (Fig....