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Pass Gate Incrementer

IP.com Disclosure Number: IPCOM000109302D
Original Publication Date: 1992-Aug-01
Included in the Prior Art Database: 2005-Mar-23
Document File: 2 page(s) / 64K

Publishing Venue

IBM

Related People

Bechade, RA: AUTHOR

Abstract

A digital incrementer scheme is described in which the carries and increments are generated using only pass gate selectors and inverters. Propagation time through the incrementer is enhanced by avoiding cascaded inverting logic circuits to realize the same Boolean result. The carry is propagated through two chains of pass gates: one for carry true (+Cin) and one for carry complement (-Cin). The carry outputs of each bit control the selection of the carry in the following bit. Incrementer blocks of various sizes can be combined to accommodate the size of the data field.

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Pass Gate Incrementer

       A digital incrementer scheme is described in which the
carries and increments are generated using only pass gate selectors
and inverters.  Propagation time through the incrementer is enhanced
by avoiding cascaded inverting logic circuits to realize the same
Boolean result. The carry is propagated through two chains of pass
gates: one for carry true (+Cin) and one for carry complement (-Cin).
The carry outputs of each bit control the selection of the carry in
the following bit.  Incrementer blocks of various sizes can be
combined to accommodate the size of the data field.

      A four-bit incrementer using the described scheme is shown in
Fig. 1. The four bits to be incremented are D0 through D3. The
incremented outputs are S0 through S3. Complementary carry inputs are
+Cin and -Cin. Complementary carry outputs are +Cout and -Cout. The
only logic circuits used are inverters and pass gates. The pass gates
have data inputs A0 and A1, and complementary selector inputs P0 and
P1.  While multiplexing pass gates are shown for purposes of
illustration, other logic circuits such as AND OR INVERT gates may be
used to perform the select function.

      Incrementer block sizes other than four bits can be constructed
by expanding or contracting the generic scheme shown in Fig. 1.
Block sizes may be selected to facilitate circuit layout.  In Fig. 2,
incrementer blocks of four, six and eight bits are combined to
realize a 32-bit incrementer....