Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Improving Performance with Automatic Interrupts

IP.com Disclosure Number: IPCOM000109311D
Publication Date: 2005-Mar-23
Document File: 3 page(s) / 42K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a new configuration option in which re-enabling interrupts has the side effect of automatically setting the "software-requested interrupt" bit. Benefits include improving the performance of networking devices.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Improving Performance with Automatic Interrupts

Disclosed is a method for a new configuration option in which re-enabling interrupts has the side effect of automatically setting the “software-requested interrupt” bit. Benefits include improving the performance of networking devices. 

Background

In a high-speed networking environment, the number of receive packets that must be processed may take more time than the driver can spend in its interrupt processing routine. For example, Windows networking certification requires that a driver spend a limited amount of time in a single deferred procedure call (DPC).  If the driver spends more time on the DPC than this limit, it cannot be certified. The reason for this requirement is that DPCs that run too long prevent other software on the system from working efficiently. Modern network operating systems seek to distribute the available processing power to multiple components of the system, rather than allowing a single component to use all of the available time.

For this reason, it is sometime necessary for a network driver to exit a DPC with unprocessed packets. When doing this, network drivers must implement some mechanism to ensure that there is an opportunity to process these packets in the future. It is not acceptable to assume that another interrupt will occur due to subsequent packet reception; there is always the possibility that all packets have been received and no further packets will arrive to trigger an interrupt. In current implementations, another interrupt is guaranteed by the driver via a software-programmable interrupt. The software driver writes to a certain register at the end of its DPC to ensure that the network interface card (NIC) interrupts at the next possible opportunity (i.e. within the bounds of its interrupt moderation scheme) so that the remaining packets may be processed at some later point.

This is not an ideal situation. Under heavy load, the driver exits nearly every DPC with unprocessed packets. Register reads and writes are extremely expensive in today’s systems, with reads being four to five times as expensive as writes (1000+ clocks in a Banias system for a read, versus 200+ for a write). This is because the writes are posted while the reads need to complete before the system can continue. In future chipsets, register writes will become as expensive as register reads because they will no l...