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High Performance BiCMOS Receiver with Self Test Mode

IP.com Disclosure Number: IPCOM000109326D
Original Publication Date: 1992-Aug-01
Included in the Prior Art Database: 2005-Mar-23
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

Adams, RD: AUTHOR [+3]

Abstract

A BiCMOS receiver for emitter-coupled logic (ECL) is described which includes both normal and self-test modes. The design requires no mode-selecting multiplexer so that self-test imposes very little penalty on performance. In the normal mode, the receiver input consists of ECL data. In the self-test mode, the input consists of CMOS data which overdrives the receiver. In either mode, the receiver differential outputs are compatible with ECL data levels.

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High Performance BiCMOS Receiver with Self Test Mode

       A BiCMOS receiver for emitter-coupled logic (ECL) is
described which includes both normal and self-test modes.  The design
requires no mode-selecting multiplexer so that self-test imposes very
little penalty on performance.  In the normal mode, the receiver
input consists of ECL data.  In the self-test mode, the input
consists of CMOS data which overdrives the receiver.  In either mode,
the receiver differential outputs are compatible with ECL data
levels.

      NPN devices Q12, Q13, Q19 and resistors R3, R4 and R5 form a
current switch input stage in the figure.  In the normal mode, the
TEST input is at a high CMOS level and PFET T15 is off.  NFET T17
is on and turns Q11 off so that there is no current in either Q10
or T14.  Current from Q19 is steered through Q12 and R3 if the
voltage at ECL input terminal IN is more positive than the voltage at
external voltage reference terminal VR, or through Q13 and R4 if IN
is more negative than VR.  True and complement differential outputs
appear at terminals RT and RC.  Q14, Q16, Q18 and R6 form a level
shifter between terminals RT and T.  Q9, Q15, Q17 and R5 form another
level shifter between RC and C.  Complementary outputs at T and C are
ECL compatible. Terminal X0 must be driven by an external reference
voltage for current sources Q19, Q11, Q18 and Q17.

      In the self-test mode, TEST is at ground so that T15 is on to
divert all Q19 collecto...