Browse Prior Art Database

Fast Bit Fuse Comparator for BiCMOS Arrays

IP.com Disclosure Number: IPCOM000109335D
Original Publication Date: 1992-Aug-01
Included in the Prior Art Database: 2005-Mar-23
Document File: 3 page(s) / 71K

Publishing Venue

IBM

Related People

Chan, Y: AUTHOR [+3]

Abstract

Fig. 1 shows the schematic of an existing cascode current switch bit comparator used for array redundancy applications. The function of this circuit is to compare an incoming address (BIT) with a preset redundancy address (FUSE). The TRUE and COMPLEMENT values of this redundancy address are generated by a fuse control circuitry not shown here. When the BIT and FUSE addresses match, the output of the comparator goes low; otherwise, the output stays high (see the truth table).

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Fast Bit Fuse Comparator for BiCMOS Arrays

       Fig. 1 shows the schematic of an existing cascode current
switch bit comparator used for array redundancy applications.  The
function of this circuit is to compare an incoming address (BIT) with
a preset redundancy address (FUSE).  The TRUE and COMPLEMENT values
of this redundancy address are generated by a fuse control circuitry
not shown here.  When the BIT and FUSE addresses match, the output of
the comparator goes low; otherwise, the output stays high (see the
truth table).

      Fig. 2 shows a new design approach for the bit comparator.
Logical operations of this circuit are similar to that of the
existing design.  However, the new approach offers an advantage of
reduced fan- out loadings on the incoming address line.

      Referring to Fig. 3, the address line in an existing design is
loaded down by 2*N of base inputs, where N is the number of
comparators used.  In the new approach (Fig. 4), the comparators
require that the bit input level be shifted down by 1 VBE.  Hence,
fan-out seen by the address line is only an additional base input;
loading of the comparators has been transferred to the emitter
follower instead.  With substantial loading reduction on the address
line, access delay penalty due to redundancy operation therefore is
minimized.