Browse Prior Art Database

Floating Point CAT TIGER Divide Implementations

IP.com Disclosure Number: IPCOM000109351D
Original Publication Date: 1992-Aug-01
Included in the Prior Art Database: 2005-Mar-23
Document File: 5 page(s) / 188K

Publishing Venue

IBM

Related People

Chu, TV: AUTHOR [+4]

Abstract

One of the goals of the floating point was to design a small, high- performance floating point unit which conformed to the IBM RISC System/ 6000* architecture. Although the float divide instruction does not occur very frequently in most benchmarks, poor divide performance can substantially degrade many of those benchmarks. Another factor in determining the divide implementation was to maintain the simplicity of design characteristics of other parts of the floating point. This type of design approach was instrumental in keeping cycle times down.

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Floating Point CAT TIGER Divide Implementations

       One of the goals of the floating point was to design a
small, high- performance floating point unit which conformed to the
IBM RISC System/ 6000* architecture.  Although the float divide
instruction does not occur very frequently in most benchmarks, poor
divide performance can substantially degrade many of those
benchmarks.  Another factor in determining the divide implementation
was to maintain the simplicity of design characteristics of other
parts of the floating point.  This type of design approach was
instrumental in keeping cycle times down.

      For the floating point, a choice was made to use a two-bit
nonrestoring division algorithm.  Although using a well known
algorithm, the "CAT" mechanism used to find the next guess is quite
different from other floating point units.
      Part 1:  Nonrestoring division algorithm (A/B)
           In the more well known restoring division algorithm, it is
necessary to restore the remainder whenever it becomes negative.
There is a possibility of having to do a second addition on any of
the N times through the loop. In the nonrestoring algorithm shown
below, the need for this second addition is eliminated by allowing
the intermediate remainder to go negative.  However, you can see that
you must be able to either add or subtract B from A.
           Step 1:  Do N Times
                If the sign of A is 0, then shift A and Q left one
position and subtract B from A; otherwise, shift A and Q left and add
B to A. If the sign of the new A is 0, set Q(LSB) to
1, otherwise, set Q(LSB) to 0.
           Step 1:  If the sign of the final A is 1, then add B to
A.

      Notice that in the one-bit algorithm, you are actually guessing
a '1' every cycle.  If the new A is negative, you subtract '1' from
the guess.  This point will be expanded in the discussion of "two-bit
division" below.
      Part 2:   Radix-4 division
           Two-bit nonrestoring division adds another level of
complexity into the algorithm.  The hardware must be able to add or
subtract multiples of B other than just 1 or 0.  Also, since the
guesses are not always '1', subtraction for a negative remainder
becomes slightly more involved.  Below is a table of the guesses
possible from our look-up table and the bits actually stored in the
quotient given the sign of the remainder.
         GUESS                      SIGN ON
                                   REMAINDER        BITS STORED
GUESS =  0 (00)                        0                00
GUESS = +1 (01)                        0                01
GUESS = +2 (10)                        0                10
GUESS = -1 (11)                     ...