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High Performance System Clock Generation within Existing Very Large Scale Integration Chips

IP.com Disclosure Number: IPCOM000109352D
Original Publication Date: 1992-Aug-01
Included in the Prior Art Database: 2005-Mar-23
Document File: 2 page(s) / 85K

Publishing Venue

IBM

Related People

Grimes, DW: AUTHOR [+3]

Abstract

This article describes an on-chip oscillator with synchronizing capabilities.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

High Performance System Clock Generation within Existing Very Large Scale Integration Chips

       This article describes an on-chip oscillator with
synchronizing capabilities.

      The ring oscillator described herein is shown in Fig. 1A within
the broken lines.  The oscillating ring contains a driver, common I/O
clock_net, receiver, two input NANDs and a delay block.  The nominal
delay of the delay book chosen determines the desired oscillation
frequency.  An XNOR and a two-input AND block enable and disable the
ring driver.  The common I/O clock_net oscillates through four states
of zero, high impedance zero, one, high impedance one, and continues
to oscillate in that sequence as shown in Fig. 1B.

      A signal sourced by the power supply +_POWER_GOOD (+_PWR_G) is
supplied to all system chips as delayed power status (200
milliseconds).  During the interval when power comes on and +_PWR_G
is zero, all system clock generators will drive one to the common I/O
SYS_CLOCK net (Fig. 1A).  When +_PWR_G switches to the active one
state, the clock generators commence with synchronized oscillation to
the SYS_CLOCK net.

      Chips sorted by actual oscillation rate of the common I/O
SYS_CLOCK reflect the actual performance expected by all the logic
circuits on the chip.  All system chips containing a clock generation
macro should be of approximately equal MHz clock oscillation rate so
that the common I/O SYS_CLOCK net transposes to high impedance state
before driving to complement.  All...