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High Performance CMOS Register Latch Bit

IP.com Disclosure Number: IPCOM000109358D
Original Publication Date: 1992-Aug-01
Included in the Prior Art Database: 2005-Mar-23
Document File: 1 page(s) / 47K

Publishing Venue

IBM

Related People

Seewann, E: AUTHOR

Abstract

Disclosed is a CMOS register latch bit which exhibits both improved performance and a packing density advantage over circuits identical or similar to those previously disclosed in (*).

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High Performance CMOS Register Latch Bit

       Disclosed is a CMOS register latch bit which exhibits
both improved performance and a packing density advantage over
circuits identical or similar to those previously disclosed in (*).

      The latch bit is shown in Fig. 1 of (*) and consists of a
pass device multiplexer (mux) driving an L1 latch which then drives
an L2 latch.  Both the performance and density improvements are due
to the fact that the conventional inverter pair latches with pass
device entry and feedback paths have been replaced by the single
inverter structure shown.

      Specific performance improvements resulting from the new
structure include the following:
      1.   Reduced and equalized data-in set-up times.  It is well
known that Din set-up times cannot be made equal for LH and HL
transitions for structures consisting of an n-channel pass gate mux
driving an inverter pair.  Equalized set-up times can be readily
achieved, however, in the disclosed structure by properly adjusting
the relative sizes of T1 and T2 to those of T3 and T4 so as
to overcome the VT loss in the input n-channel pass mux.  This has
the effect of decreasing the LH set-up time with little increase of
HL set-up time.  Equalization to within 50 psec can typically be
realized.
      2.   L2 performance is also improved.  This is due to the fact
that since the L2 latch is driven through complementary pass devices,
transistors T5-T8 can, therefore, be...