Browse Prior Art Database

Floating Point Unit Divide Counter Implementation using the Normalize Register

IP.com Disclosure Number: IPCOM000109359D
Original Publication Date: 1992-Aug-01
Included in the Prior Art Database: 2005-Mar-24
Document File: 2 page(s) / 67K

Publishing Venue

IBM

Related People

Chu, TV: AUTHOR [+4]

Abstract

The Floating Point implements a Radix-4 nonrestoring organ division algorithm. This algorithm uses the data flow for a fixed number of cycles, until it extracts the necessary bits for the quotient, then stops further iterations. Normally, there would be a dedicated counter to indicate the number of iterations completed. When the counter reaches the required limit, it would signal the stop of divide iterations.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 83% of the total text.

Floating Point Unit Divide Counter Implementation using the Normalize Register

       The Floating Point implements a Radix-4 nonrestoring
organ division algorithm.  This algorithm uses the data flow for a
fixed number of cycles, until it extracts the necessary bits for the
quotient, then stops further iterations.  Normally, there would be a
dedicated counter to indicate the number of iterations completed.
When the counter reaches the required limit, it would signal the stop
of divide iterations.

      The problem is the cost of building a dedicated counter.  This
disclosure avoids the need to build such a counter.

      On the start up of the divide instruction, two bits are placed
in the Normalize register, the register used to sample the quotient,
as a flag to signal the end of divide iterations.  Each divide
iteration extracts two bits of the quotient.  The result shifts left
two bit positions every cycle to make room for the next two bits of
the quotient in the next iteration.  This also moves the flag bits to
the left two bit positions every iteration.  When the flag bits spill
out of the result register, it is a signal that the iterations are
finished and need not continue any further.

      Note: Zeroing the normalize register for all bits above the
"insert" position is obviously required.  The normalizer below this
register is able to produce all zeros.  Since the insertion is done
on the feedback path, we are able to zero all required...