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Cell Efficient Growable RAM FIFO Design for Computer Systems

IP.com Disclosure Number: IPCOM000109360D
Original Publication Date: 1992-Aug-01
Included in the Prior Art Database: 2005-Mar-24
Document File: 3 page(s) / 103K

Publishing Venue

IBM

Related People

Le, PT: AUTHOR [+2]

Abstract

Described is a circuit implementation to provide a circuit cell efficient growable random access memory (GRAM) half-duplex first-in, first- out (FIFO) function. The circuit is an improvement over existing circuits in that it provides data buffering between a 32-bit computer system and an 8-bit parallel port interface with fewer cells.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 57% of the total text.

Cell Efficient Growable RAM FIFO Design for Computer Systems

       Described is a circuit implementation to provide a
circuit cell efficient growable random access memory (GRAM)
half-duplex first-in, first- out (FIFO) function.  The circuit is an
improvement over existing circuits in that it provides data buffering
between a 32-bit computer system and an 8-bit parallel port interface
with fewer cells.

      Typically, the size of a FIFO design of 148 bytes plus 1-bit of
parity per byte requires a large number of circuit cells.  The
concept described herein enables the number of cells to be reduced
and also provides a data size conversion of 32 bit to 8 bit and 8
bit to 32 bit functions at each end of the pipe.  The FIFO design
utilizes two interface buses and the RAM to reduce the cell
requirement.

      Fig. 1 shows the FIFO data path circuit elements.  Standard
cell 36-bit X 37 GRAM 10 is incorporated along with data
steering/controller 11.  The input/output (I/O) data of RAM 12 is a
double word or 32-bits.  The input data is collected into 4 bytes
registers 13 after being processed through selectors 14 and 9-bit
registers 15.  If 4 bytes register 13 is full, a write (WR) pulse
from WR address generator 16 is automatically generated and the data
is stored into RAM 12.  Fig. 2 shows a diagram of the RAM clock
timing.  Node 1 shows the timing relationship of the first WR
address.  The WR address is then automatically indexed to the next
GRAM addres...