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Ensuring a Proper and Complete Processor Reset

IP.com Disclosure Number: IPCOM000109362D
Original Publication Date: 1992-Aug-01
Included in the Prior Art Database: 2005-Mar-24
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Bealkowski, R: AUTHOR [+3]

Abstract

This article describes a hardware mechanism which ensures the proper and complete reset of a processor such as the Intel 80486.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 86% of the total text.

Ensuring a Proper and Complete Processor Reset

       This article describes a hardware mechanism which ensures
the proper and complete reset of a processor such as the Intel 80486.

      To solve the reset problem on some personal computers using the
Intel 80486, a hardware mechanism must be added to ensure that a
processor reset occurs correctly.

      One design solution is to add circuitry to an 80486 system
which allows it to behave like the Intel 80386 system during a reset.
Example hardware to perform this is shown in Fig. 1.  A processor
reset or Gate A20 will cause A20M to be set.  This ensures that the
A20M     is in the state required for a processor reset to occur.
This circuit does not ensure that the 80486 will begin fetching
instructions from the correct location.

      The complete solution to properly resetting the 80486 processor
is shown in Fig. 2.  This hardware provides the correct support for a
successful processor reset.  This circuit ensures that the A20M
signal is in the correct state during a reset and maintains the
correct state until the 80486 is properly executing in real mode.
This hardware guarantees that the processor will begin fetching
instructions from the correct location.  Either a processor reset or
Gate A20 will set A20M#.  Even with the processor reset and Gate A20
cleared, A20M     will continue to be set until a valid A31 of zero
(A31 zero and address strobe (ADS#) active) is detected signifying
the...