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Write Lockout Mechanism to Provide Testability in a Free Running Counter Application

IP.com Disclosure Number: IPCOM000109375D
Original Publication Date: 1992-Aug-01
Included in the Prior Art Database: 2005-Mar-24
Document File: 2 page(s) / 77K

Publishing Venue

IBM

Related People

Clarke, GL: AUTHOR [+2]

Abstract

This article describes a method and hardware implementation for use in a computer system which allows a free-running counter to be tested by power-on self-test (POST) software by permitting writes in test mode. Use of the counter by applications is read only.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 55% of the total text.

Write Lockout Mechanism to Provide Testability in a Free Running Counter Application

       This article describes a method and hardware
implementation for use in a computer system which allows a
free-running counter to be tested by power-on self-test (POST)
software by permitting writes in test mode.  Use of the counter by
applications is read only.

      A 32-bit free-running timer is one function usually provided
for use by software/applications developers.  The specification of
the timer states that in normal operation the counters should be
free-running with no capability of loading a desired count.  In other
words, the timer should count from 00000000H up to FFFFFFFFH and then
wrap around back to 00000000H and start again.  Without the
capability of loading the timer with a desired count value and
allowing it to count, POST programmers did not have a mechanism to
test the timer during setup.  The technique disclosed herein provides
testability to the timer while still allowing it to operate in a
free-running mode in normal operation.

      A write lockout mechanism which utilizes two bits in a register
and some control logic incorporates a test mode within the 32-bit
timer which gives the POST programmer the ability to test the timer
during setup.  The figure shows the write lockout mechanism as
incorporated in the 32-bit timer design.
      Register 4B Bit 0 -- P_DISABLE_LOAD:
This bit when set to 1 disables test mode and blocks writes (load...