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High Speed Level Sensitive Scan Design Clock Generation and Synchronization

IP.com Disclosure Number: IPCOM000109385D
Original Publication Date: 1992-Aug-01
Included in the Prior Art Database: 2005-Mar-24
Document File: 3 page(s) / 131K

Publishing Venue

IBM

Related People

Leininger, JC: AUTHOR

Abstract

This article describes a circuit arrangement which provides high-speed clocking for multiple very large-scale integration (VLSI) chips where the oscillator pulse width is only 1.5 times the minimum pulse width for latch clocks.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

High Speed Level Sensitive Scan Design Clock Generation and Synchronization

       This article describes a circuit arrangement which
provides high-speed clocking for multiple very large-scale
integration (VLSI) chips where the oscillator pulse width is only 1.5
times the minimum pulse width for latch clocks.

      In order to minimize pulse shrinking and clock skew between
chips, the oscillator signal is driven to all chips to form the clock
and one chip provides the L1 and L2 clock synchronization (sync)
signal and the A cycle and B cycle control signal.  These signals
guarantee that the oscillator pulse representing the L1 clock on the
master chip will also represent the L1 clock on all other chips and
the A cycle and B cycle occur at the same time on all chips.  The
exception to this is when power-on reset is active.  Power-on reset
causes the outputs of all chips to float so that the value of the
sync signals is indeterminate.  In addition, each chip must operate
so that initialization and clean-up functions are performed on each
chip during power-on reset.  This design also provides multiple C
clocks (L1 clocks) for 22* latches (Fig. 2) that are used in the
design and the number of stages through which the oscillator must
pass are minimized to reduce clock skew between chips and to minimize
pulse shrinkage.

      Fig. 1 shows the oscillator from which all clocks are
generated, the clock control signals and the L1 and L2 sync line
along with the A cycle and B cycle control sync line.  Multiple A and
B cycles may be required by the design.

      The B and C clocks shown in Fig. 1 are generated by ANDing the
oscillator delayed with the toggle L2 latch delayed to generate the
proper timing relationships.  Additionally, ANDing the AS clock and
not test mode provides the alternate C clock, ANDing the B clock
provides the active B clock and ANDing the C clock generates the
active C clock when combined with the oscillator and the appropriate
phase of the delayed toggle L2 latch.

      The A cycle B cycle signal is timed to change just prior to the
acti...