Browse Prior Art Database

At Overlap Command Circuit

IP.com Disclosure Number: IPCOM000109388D
Original Publication Date: 1992-Aug-01
Included in the Prior Art Database: 2005-Mar-24
Document File: 2 page(s) / 74K

Publishing Venue

IBM

Related People

Asano, H: AUTHOR [+4]

Abstract

Disclosed is a circuit for an overlap command procedure for HDD (Hard Disk Drive) with PC AT* interface. This circuit enables an overlap command to start to be executed with work of a hardware and without work of a microprocessor. Therefore, the performance of data transfer is improved.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

At Overlap Command Circuit

       Disclosed is a circuit for an overlap command procedure
for HDD (Hard Disk Drive) with PC AT* interface.  This circuit
enables an overlap command to start to be executed with work of a
hardware and without work of a microprocessor.  Therefore, the
performance of data transfer is improved.

      The characteristic of this invention is to have 3 register
sets.  These are Real Time register set, Hold register set and MPU
Read register set. Each register set includes Sector Count register,
Sector Number register, Cylinder Low register, Cylinder High register
and Drive Head register of command Block registers, respectively.
Parameters of a command from a host are set into these 3 register
sets as described below.

      The figure shows the circuit block diagram of this invention.

      Real Time register set (1) is a set of registers which a host
writes parameters into by HIOW signal or reads parameters from by
HIOR signal. The parameters of this register set vary at real time by
INC/DEC signal according to the data transfer.  As the data transfer
starts by the hardware and parameters of this register set vary from
initial parameters, a microprocessor cannot read parameters from this
register set to know initial parameters that a host wrote into.

      Hold register set (2) is a set of registers which a host writes
parameters into by HIOW signal.  Parameters are written into this
register set at the same time when t...