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Selective Germanium Etch Emitter Opening

IP.com Disclosure Number: IPCOM000109407D
Original Publication Date: 1992-Aug-01
Included in the Prior Art Database: 2005-Mar-24
Document File: 4 page(s) / 188K

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Related People

Bestwick, TD: AUTHOR [+4]


A selective RIE etch for Silicon over SiGe layers to self-align an emitter opening with a heavily doped extrinsic base layer is disclosed.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Selective Germanium Etch Emitter Opening

       A selective RIE etch for Silicon over SiGe layers to
self-align an emitter opening with a heavily doped extrinsic base
layer is disclosed.

      This article specifically addresses the problem of
self-aligning a heavily doped extrinsic base layer to an emitter
opening.  The application is to high performance epitaxial Si or
SiGe-base bipolar transistors.  The finished structure is very
similar to a double-poly advanced bipolar device (ATX).  The details
given below are for one set of layer thicknesses.  These values are
for illustration and they can be varied.

      The starting point is a silicon bipolar process with isolation,
resistors, etc.  This article assumes all these steps have been
previously completed.  The article will be presented for NPNs, but it
applies as well to PNP with a reversal of the dopant species.  A
blanket epitaxial deposition of 5 layers takes place.  The layers are
indicated in Fig. 1 and numbered in the same sequence.  These layers
are: (1) intrinsic base, (2) 10 nm P buffer layer, (3) 30 nm 3 X
1021cm-3, (4) 30 nm 3 X 1021cm-3 20% Ge layer, and (5) 100 nm 3
X 1021cm-3 layer.  A 100 nm dielectric layer of oxide (6) is
deposited on top of the stack and then a masking step is used to
define the outer edge of the extrinsic base (Fig. 2).  A layer of
nitride 7 is deposited (Fig. 3) and the emitter opening is defined
lithographically.  The dielectrics are etched with a standard RIE
etch exposing the layer 5 of the epitaxial stack.  A selective RIE
etch that etches silicon selective to SiGe layers with 10-50% Ge with
10-15 etch selectivity is now used to etch layer 5.  This etch is
discussed below.  This etch continues down through the stack until it
reaches layer 4 and stops on the 20% SiGe layer.

      The etching process is changed to give a high selectivity of
SiGe to Si with a non-hydrogen containing etch gas mixture.  The etch
may be a plasma etch and continues through the heavily doped P++20%
SiGe layer stopping in the P++ silicon layer.  Since Ge snowplows
during oxidation at the interface, it is important to remove all the
20% SiGe layer and etch into the heavily doped layer 3.  The
structure at this point is shown in Fig. 4.

      A 600~C high-pressure oxidation is now used to grow a
passivating oxide over...