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Browse Prior Art Database

Fetch Store Data Buffer for High Data Rate Dynamic Random Access Memory

IP.com Disclosure Number: IPCOM000109420D
Original Publication Date: 1992-Aug-01
Included in the Prior Art Database: 2005-Mar-24
Document File: 3 page(s) / 117K

Publishing Venue

IBM

Related People

Aichelmann Jr, FJ: AUTHOR [+3]

Abstract

On-chip interleave capability and buffering of both read and write data are combined to result in a dynamic random access memory (DRAM) architecture having high data rate capability without requiring interleaving with multiple memory cards. An input/output (I/O) interface structure and timing diagram are presented which overcome system granularity inhibitions to interleaving when small numbers of dense memory chips are used for main stores.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 57% of the total text.

Fetch Store Data Buffer for High Data Rate Dynamic Random Access Memory

       On-chip interleave capability and buffering of both read
and write data are combined to result in a dynamic random access
memory (DRAM) architecture having high data rate capability without
requiring interleaving with multiple memory cards.  An input/output
(I/O) interface structure and timing diagram are presented which
overcome system granularity inhibitions to interleaving when small
numbers of dense memory chips are used for main stores.

      Referring to Fig. 1, address inputs 10 to decoder 12 select a
DRAM address within an array 14 having self-timed partitions 16 which
allow an access to one partition to be overlapped with cycles of one
or more previously selected partitions.  A row access select (RAS)
input 18 through RAS amplifier 20 loads a fetch buffer 22 by
coincidence of a fetch input to fetch/store (F/S) input 24 through
F/S amplifier 26 to line 28.  After buffer 22 is loaded, a transfer
toggle input 30 to toggle amplifier 32 begins.  A copy operation from
fetch buffer 22 to read buffer 38 is thus triggered on a next toggle
edge, as shown in the timing diagram of Fig. 2.  Two bit toggle
counter 34 increments on each toggle transition to serially transfer
data through multiplexer (MUX) 36 from read buffer 38 to I/O buffer
40 and I/O 42 when read/write (R/W) input 44 through W/R amplifier 46
is in read polarity (high), thus selecting line 48.  A positive going
signal...