Browse Prior Art Database

Planarization of Tungsten Filled Vias with Stringent Topography

IP.com Disclosure Number: IPCOM000109464D
Original Publication Date: 1992-Aug-01
Included in the Prior Art Database: 2005-Mar-24
Document File: 1 page(s) / 42K

Publishing Venue

IBM

Related People

Basavaiah, S: AUTHOR [+3]

Abstract

Disclosed is a method for fabricating a planar insulator film, such as silicon dioxide, which contains vias or studs of Tungsten. Since the insulator is typically deposited over topography due to underlying active device areas or interconnect metallurgy, a preplanarization of the insulator film using RIE-etch back or chem. mech. polishing typically precedes the W deposition step. In the present invention, however, a simpler process is proposed. Tungsten is blanket or selectively deposited over the unplanarized oxide film, effectively filling the predrilled vias. Then, a chem. mech. polish process which planarizes Tungsten and oxide simultaneously is applied to generate the final, desired, structure. In general, the process requirement for this step is roughly equivalent chem. mech.

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Planarization of Tungsten Filled Vias with Stringent Topography

      Disclosed is a method for fabricating a planar insulator film,
such as silicon dioxide, which contains vias or studs of Tungsten.
Since the insulator is typically deposited over topography due to
underlying active device areas or interconnect metallurgy, a
preplanarization of the insulator film using RIE-etch back or chem.
mech. polishing typically precedes the W deposition step.  In the
present invention, however, a simpler process is proposed.  Tungsten
is blanket or selectively deposited over the unplanarized oxide film,
effectively filling the predrilled vias.  Then, a chem. mech. polish
process which planarizes Tungsten and oxide simultaneously is applied
to generate the final, desired, structure.  In general, the process
requirement for this step is roughly equivalent chem. mech. removal
rates for Tungsten and oxide over topography.  Aside from process
simplification by eliminating a separate planarization step, the
invention reduces the amount of overetch required in the initial RIE
definition of studs.

      Disclosed anonymously.