Browse Prior Art Database

Programmable VLSI Clock Generator

IP.com Disclosure Number: IPCOM000109485D
Original Publication Date: 1992-Sep-01
Included in the Prior Art Database: 2005-Mar-24
Document File: 2 page(s) / 65K

Publishing Venue

IBM

Related People

Cronauer, TD: AUTHOR [+2]

Abstract

A two-chip external clock generator is disclosed which maintains very accurate control over clocks driving random logic and cache memories on various VLSI chips.

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This is the abbreviated version, containing approximately 100% of the total text.

Programmable VLSI Clock Generator

       A two-chip external clock generator is disclosed which
maintains very accurate control over clocks driving random logic and
cache memories on various VLSI chips.

      Referring to Fig. 1, a high-speed input clock (C) signal is
supplied to a five top digital delay line which provides five output
signals (C15-C75), each separated by a predetermined time period.
The five output signals and the input signal clock signal are fed to
a programmable array which facilitates the generation of six VLSI
clocks as shown in Fig. 2.  The programmable array logically combines
the appropriate rising and falling output signals to generate an
optimal VLSI clock.  The generation of the clock signals in this
manner facilitates tight control over the signals which are supplied
to the various VLSI chips.  This technique resulted in a two to three
fold speed improvement when compared to a technique using internal
clock generation.  Moreover, this technique allows the clock signals
to be changed merely by changing the programming of the array.