Browse Prior Art Database

Method to Fabricate FET Devices

IP.com Disclosure Number: IPCOM000109495D
Original Publication Date: 1992-Sep-01
Included in the Prior Art Database: 2005-Mar-24
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

Basavaiah, S: AUTHOR [+2]

Abstract

Disclosed is a new FET fabrication technique using silicide, such as CoSi2 or polysilicon, as the diffusion source to form the source/drain junctions of the FET devices. The major advantage of this process is to achieve fully planarized device structure through the entire process. The processing steps are described as follows: 1. Deposit cobalt (or poly), RTA to form cobalt silicide (CoSi2), then implant diffusion dopant into cobalt (see Fig. 1). 2. Deposit thick oxide, RIE gate, contact at the same time, fill the opening with polyimide. 3. Selectively open the gate openings and etch the silicide away (see Fig. 2). 4. Clean polyimide, deposit dielectric and RIE to form sidewall (see Fig. 3). 5. Deposit or grow gate oxide, anneal to diffuse out dopant to form junctions (see Fig. 4). 6.

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Method to Fabricate FET Devices

       Disclosed is a new FET fabrication technique using
silicide, such as CoSi2 or polysilicon, as the diffusion source to
form the source/drain junctions of the FET devices.  The major
advantage of this process is to achieve fully planarized device
structure through the entire process.  The processing steps are
described as follows:
1.  Deposit cobalt (or poly), RTA to form cobalt silicide (CoSi2),
then implant diffusion dopant into cobalt (see Fig. 1).
2.  Deposit thick oxide, RIE gate, contact at the same time, fill the
opening with polyimide.
3.  Selectively open the gate openings and etch the silicide away
(see Fig. 2).
4.  Clean polyimide, deposit dielectric and RIE to form sidewall (see
Fig. 3).
5.  Deposit or grow gate oxide, anneal to diffuse out dopant to form
junctions (see Fig. 4).
6.  Deposit gate material and planarize (see Fig. 5).