Browse Prior Art Database

Backward Averaging Digital Phase Locked Loop Circuitry

IP.com Disclosure Number: IPCOM000109500D
Original Publication Date: 1992-Sep-01
Included in the Prior Art Database: 2005-Mar-24
Document File: 5 page(s) / 235K

Publishing Venue

IBM

Related People

Butzer, DC: AUTHOR

Abstract

Described is a process and circuit implementation for data recording applications in a computer system using backward averaging digital phase-locked loop (DPLL) circuitry.

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Backward Averaging Digital Phase Locked

Loop

Circuitry

       Described is a process and circuit implementation for
data recording applications in a computer system using backward
averaging digital phase-locked loop (DPLL) circuitry.

      In prior art, phase-locked loop (PLL) implementation utilized
analog circuitry.  However, the analog circuitry required
verification of calibration after final assembly of the subsystem.
The concept described herein uses backward averaging DPLL circuitry
that eliminates the need to verify the calibration by utilizing an
asynchronous read data signal from the disk drive to generate a
window along with a standard data signal that can be used to decode
the signal information.  The DPLL can be easily implemented using
existing logic circuitry.  The use of a backward DPLL circuit
pertaining to a disk subsystem is described herein, although the
concept can be applicable to other data recovery applications, such
as communications data recovery.

      In disk drive subsystems, the aspects of bit shift must be
considered.  Typically, a bit shift occurs when two closely written
bits repel each other on the magnetic media.  In addition, a bit
shift can occur when two widely spaced bits are pushed together by
surrounding bits.  Figs. 1A, 1B and 1C show an example of a bit shift
in the data read from a disk drive.  The window clock signal (Fig.
1A), the data signal written to the drive (Fig. 1B) and data read
from the drive (Fig. 1C) with the shift that can occur are shown. Bit
shift is often measured as a percent of the normal window size.  The
window signal is for a 500K bit/second data rate, or 1 ms long per
phase.  Therefore, the bit shift is 20% for each bit.  The close bits
repel each other 200 ns and the far apart bits move 200 ns closer to
each other.

      Another aspect to be considered is the speed variations of the
drive.  An average speed variation occurs when the average speed of
the spinning disk is different during the read operation than during
the write operation.  Also, an instantaneous speed variation (ISV)
can occur when the speed of the spinning disk changes during a read
operation.  Both the average and ISV can be measured as a percentage
deviation from the nominal.  Fig. 2A shows the window for the average
speed variation.  Fig. 2B shows the read data signal with a 20%
average speed increase from its nominal of 1 ms per window phase.
The window for the ISV is shown in Fig. 2C and the read data signal
with a 20% increase and then a 20% decrease in speed is shown in Fig.
2D.  The window refers to the length of one phase of the window
signal which is half of the period of the square wave formed by the
signal.  The figure of 20% is shown for graphic representation,
whereas, the actual variations would be on the order of only 3%.  The
read data signals are signals with a zero percent bit shift.

      The first part of the basic operation of the DPLL is to cr...