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VLSI Metals Management Evaluation System for Additive and Subtractive Metal Technologies

IP.com Disclosure Number: IPCOM000109502D
Original Publication Date: 1992-Sep-01
Included in the Prior Art Database: 2005-Mar-24
Document File: 6 page(s) / 301K

Publishing Venue

IBM

Related People

Conway, JF: AUTHOR [+3]

Abstract

It has become customary in the manufacturing of VLSI, to use the manufactured wafers as process evaluators. At the completion of each critical step there is a go no go inspection or a verification of the process integrity through multiple measurement on several wafers. The collected data is used as tracking of the line behavior and plotted to describe process stability and forecast process yield values. This lengthy process requires handling of wafers of increasing value as they get closer to the end of the process, with danger of losses and increase in the overall product contamination levels. In addition, there is the need for inspectors, microscopes and in line-handling equipment; wafer throughput is lessened due to operational delay.

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VLSI Metals Management Evaluation System for Additive and Subtractive Metal Technologies

       It has become customary in the manufacturing of VLSI, to
use the manufactured wafers as process evaluators.  At the completion
of each critical step there is a go no go inspection or a
verification of the process integrity through multiple measurement on
several wafers.  The collected data is used as tracking of the line
behavior and plotted to describe process stability and forecast
process yield values.  This lengthy process requires handling of
wafers of increasing value as they get closer to the end of the
process, with danger of losses and increase in the overall product
contamination levels.  In addition, there is the need for inspectors,
microscopes and in line-handling equipment; wafer throughput is
lessened due to operational delay.  No independent measurement of
process latitude and/or extendability is possible, since valuable
wafers cannot be used for experimentation.  The "process centering"
may just be a repetitive result obtainable in a marginal system
set-up.  No effort is made to evaluate/control the process with
independent process indicators, to lessen and eliminate the need for
in line inspection steps.

      Metal levels are a typical example of these proceedings.  They
are performed toward the end of the process, on very expensive
product.  The metal levels are used by VLSI fabricators to form
device contacts, create interdevice wiring and interlevel linking,
with several layers up to the global wiring.

      Metal structure integrity and continuity is key to the final
device success.  The interconnecting metals (i.e., M1 and M2 levels
in VLSI manufacturing)  are vacuum deposited and lifted off.  This
process has been described in other publications covering many
aspects from stencil preparation, evaporation/deposition of metal and
the lifting off of unwanted metal areas.  Here again, the layers are
inspected prior and post the lift-off process.

      Usually the metal is deposited in a vacuum system, using as a
source, molten material; films result from nucleation/condensation of
metal atoms on the receiving surface.  There are many factors which
influence the proper formation of a metal line over other lines or
over a via hole.  Evaporation rate, nature of the metal being
deposited, the temperature of the receiving substrate during the
evaporation process and the source/wafer line of sight deposition
angle.  Defective techniques may lead to poor metal adhesion,
non-uniform thickness along stenciled area, and excessive filling of
stencils' slopes.  Also, deposited metal lines tend to form
structural discontinuities when crossing over a topography step;
examples being where the metal is required to pick up an underlaying
layer (contact hole) or over a previously deposited metal layer (M2
over M1).  These structural discontinuities will affect chip
reliability and result in poorly performin...