Browse Prior Art Database

Memory Arbitration with Out of Order Execution in Conjunction with a RISC System

IP.com Disclosure Number: IPCOM000109503D
Original Publication Date: 1992-Sep-01
Included in the Prior Art Database: 2005-Mar-24
Document File: 3 page(s) / 132K

Publishing Venue

IBM

Related People

Muhich, JS: AUTHOR [+2]

Abstract

This article describes improved memory access via out of order execution by allowing read operations (loads and fetches) to be performed before stores while keeping the memory system consistent.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Memory Arbitration with Out of Order Execution in Conjunction with a RISC System

       This article describes improved memory access via out of
order execution by allowing read operations (loads and fetches) to be
performed before stores while keeping the memory system consistent.

      The RISC processor memory queue arbitration involves processing
and prioritizing memory requests between three memory queue
locations: Memory Address Register A (MARA), Memory Address Register
B (MARB), and the cache.  Requests from these three locations vie for
position in the Current Memory Address Register (CMAR).  The CMAR
holds the next request to be issued to memory.  The figure shows the
basic memory queue structure.

      The RISC processor memory queue arbitration is comprised of
seven levels of arbitration.  Each arbitration level is comprised of
a specific request class.  The arbitration classes and their priority
levels were selected in order to optimize overall system performance
and to maintain data integrity within the system.

      Requests within a specific arbitration class are performed in
sequence out to main memory.  That is, while arbitration within the
memory queue is based on the level of each class priority, requests
within each class are performed in the sequence received into the
memory queue.

      Arbitration of memory request into the CMAR is performed every
cycle.  An arb request is generated for each request in the memory
queue with the highest level arb request being granted.  Whether or
not this request actually gets loaded into the CMAR depends on the
availability of the CMAR.  If the CMAR can accept the request, the
request is loaded into the CMAR and the appropriate memory request is
made next cycle.  If the CMAR is busy and cannot accept the request,
the granted request is not loaded into the CMAR and the memory queue
is re-arbed on the following cycle.

      In particular, Old Arb Request and DMA Arb Request help improve
system DMA performance by raising the priority of DMA requests in the
memory queue under certain conditions.  Memory system performance is
improved with the Load hit Reload Arb Request by maintaining DRAM
page mode access when data from the same cache line is requested from
memory.

      The following is a list of arbitration classes for the RISC
processor memory queue and describes the priorities that...