Browse Prior Art Database

Sense and Isolate Circuit

IP.com Disclosure Number: IPCOM000109529D
Original Publication Date: 1992-Sep-01
Included in the Prior Art Database: 2005-Mar-24
Document File: 2 page(s) / 73K

Publishing Venue

IBM

Related People

Davis, A: AUTHOR [+2]

Abstract

Features of this circuit include: 1) the node which gets pulled low only has to discharge sense node capacitance, and during the sensing operation, bit line capacitance is automatically isolated from the critical sense node resulting in high performance, 2) a bit line signal is available at sense line sensing devices prior to setting a latch leading to excellent noise margin, and 3) only a single signal is required to operate the circuit and to isolate it from the bit lines.

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Sense and Isolate Circuit

       Features of this circuit include: 1) the node which gets
pulled low only has to discharge sense node capacitance, and during
the sensing operation, bit line capacitance is automatically isolated
from the critical sense node resulting in high performance, 2) a bit
line signal is available at sense line sensing devices prior to
setting a latch leading to excellent noise margin, and 3) only a
single signal is required to operate the circuit and to isolate it
from the bit lines.

      Referring to the figure, sensing devices referred to above are
N-type devices T2 and T4.  The latch is comprised of n-type devices
T6 and T8 and P-type devices T3 and T5.

      Initially input node SET is low, devices T1 and T7 are on,
output nodes SAT and SAC are at an equal potential of high voltage
supply level VH since device T9 is also on.  When SET goes high,
devices T1, T7, and T9 go off.

      During cell read operations, either node BLT or BLC are pulled
down depending upon the data stored.  As SET goes high, node X
discharges to ground through device T10.  Nodes SAT and SAC are
discharged via T6, T8, T2, and T4.  As SAT or SAC approaches a PFET
threshold below potential of node BLC or BLT, either T3 or T5 turns
on to pull SAT or SAC to BLT or BLC level while the other sense
node continues to go to ground potential.  Also, the latch process is
further enhanced by having bit line signal BLT appear across device
T4 and signal BLC ap...