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ECL/CMOS Level Converter and Buffer for One and Two Port Random Access Memories

IP.com Disclosure Number: IPCOM000109539D
Original Publication Date: 1992-Sep-01
Included in the Prior Art Database: 2005-Mar-24
Document File: 2 page(s) / 87K

Publishing Venue

IBM

Related People

Bonges, HA: AUTHOR [+2]

Abstract

A bipolar/complementary metal oxide silicon (BiCMOS) circuit is described which provides high-speed emitter coupled logic (ECL) to CMOS level conversion and true/complement signal generation. The circuit can be used in both one and two port random access memory (RAM) designs.

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This is the abbreviated version, containing approximately 69% of the total text.

ECL/CMOS Level Converter and Buffer for One and Two Port Random Access Memories

       A bipolar/complementary metal oxide silicon (BiCMOS)
circuit is described which provides high-speed emitter coupled logic
(ECL) to CMOS level conversion and true/complement signal generation.
The circuit can be used in both one and two port random access memory
(RAM) designs.

      First, the figure is referenced to describe single-port
operation.  Inputs ECT, ECC, and CLK are ECL inputs.  When CLK goes
low, current from NPN transistor Q3 is switched from Q4 to either Q1
or Q2, depending on whether input ECT or ECC from the receiver is
high.  Either node A or B (which are both precharged high) is
discharged to a level set up by clamp transistor Q5.  The clamp
voltage is set to a level to guarantee that devices Q1 and Q2 do not
saturate.  Node C or D is then charged to high supply level Vdd and
true output Tout or complement output Cout, that are normally low,
charge to about a base-emitter level (Vbe) below Vdd.  To reset the
circuit, CLK goes high switching the current from Q3 into Q4.  Input
RS1 is then pulsed low to reset node A or B to Vdd followed by
input RS2 pulsing high to reset node C or D and Tout or Cout to
ground.

      Two single-port cells per bit may be used to provide a fast
first access soft error rate immune two-port RAM design.  This
approach requires that cells written in either port be updated in the
other port.  This is done by pipelining two...