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Growth of Sub-microscopic Josephson Junction Array and One Dimensional Superconducting Devices

IP.com Disclosure Number: IPCOM000109552D
Original Publication Date: 1992-Sep-01
Included in the Prior Art Database: 2005-Mar-24
Document File: 2 page(s) / 103K

Publishing Venue

IBM

Related People

Gupta, A: AUTHOR

Abstract

Many of the anticipated microelectronic applications of the high temperature superconductors involve Josephson junctions, or novel device structures which can exploit the anisotropic properties of these materials. The extremely small coherence length (N0.2-2 nm) in these materials has made it difficult to fabricate reproducible junctions with the required sharp interfaces. In general, the most advantageous geometry is to have the barrier layer with the current flow in the a-b plane, so as to take advantage of the longer coherence length in the plane. However, junctions in this geometry cannot be easily fabricated. Disclosed herein is a growth procedure which has the potential of directly producing ultra-small, series-connected junctions.

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Growth of Sub-microscopic Josephson Junction Array and One Dimensional Superconducting Devices

       Many of the anticipated microelectronic applications of
the high temperature superconductors involve Josephson junctions, or
novel device structures which can exploit the anisotropic properties
of these materials.  The extremely small coherence length (N0.2-2 nm)
in these materials has made it difficult to fabricate reproducible
junctions with the required sharp interfaces.  In general, the most
advantageous geometry is to have the barrier layer with the current
flow in the a-b plane, so as to take advantage of the longer
coherence length in the plane.  However, junctions in this geometry
cannot be easily fabricated. Disclosed herein is a growth procedure
which has the potential of directly producing ultra-small,
series-connected junctions.  Additionally, these one-dimensional
structures could be exploited for other device applications. The
method is similar to what has been used recently to grow AlAs/GaAs
submonolayer superlattices on vicinal (001) GaAs (*).

      The proposed method would involve deposition of a
superconducting oxide, like YBa2Cu3O7 (YBCO) and an insulating or
semiconducting oxide, like PrBa2Cu3O7 (PBCO), on vicinal (001) SrTiO3
(lattice constant, c, 0.3905 nm).  For realizing the vertical
structures it is important that growth occurs uniformly and laterally
from the atomic step edges (edge-flow) during deposition.  For SrTiO3
substrates with small misorientation angles (0.25-0.50o), the mean
distance between atomic steps, d, will be 500-1000 o.  Under prope...