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Improved Lateral pnp and the Fabrication Method Therefore

IP.com Disclosure Number: IPCOM000109564D
Original Publication Date: 1992-Sep-01
Included in the Prior Art Database: 2005-Mar-24
Document File: 3 page(s) / 133K

Publishing Venue

IBM

Related People

Chuang, C: AUTHOR [+5]

Abstract

Disclosed in Fig. 1 is a lateral pnp transistor with enhanced performance by adding minimum process complexity to a conventional double-poly npn process. The new lateral pnp utilizes a sidewall spacer to form the base. The base-width is primarily determined by the sidewall thickness instead of the lithography capability, therefore narrow base-width can easily be achieved. Furthermore, the resulting base profile is naturally graded, with higher doping concentration at the emitter-base junction. The latter provides not only a high emitter-collector punch-through voltage but also an internal drift field, which is lacking in the 'free' epi-base lateral pnp, to aid the holes in traversing through the base.

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Improved Lateral pnp and the Fabrication Method Therefore

       Disclosed in Fig. 1 is a lateral pnp transistor with
enhanced performance by adding minimum process complexity to a
conventional double-poly npn process.  The new lateral pnp utilizes a
sidewall spacer to form the base.  The base-width is primarily
determined by the sidewall thickness instead of the lithography
capability, therefore narrow base-width can easily be achieved.
Furthermore, the resulting base profile is naturally graded, with
higher doping concentration at the emitter-base junction.  The latter
provides not only a high emitter-collector punch-through voltage but
also an internal drift field, which is lacking in the 'free' epi-base
lateral pnp, to aid the holes in traversing through the base.

      The key process steps for fabricating the pnp is described in
Figs. 1 (a)-(f).  After the collector reach-through (RT) implantation
step for npn is done (Fig. 1(a)), a composite layer of oxide/nitride
is deposited.  Photoresist is then coated and developed using a mask
(LN) (Fig. 1(b)), followed by combined dry and wet etch processes to
open a window for base formation.  After the base ion implantation/
annealing step, a disposable sidewall spacer is built as shown in
Fig. 1(c).  Subsequent emitter formation is done by p-type ion
implantation, which will be safely spaced out from the base dopants.
At this moment, a deep p-type implant pocket can also be added to
reduce the minority charge storage underneath the emitter opening.
Th...