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Shift Register Latch for Peak Power Reduction

IP.com Disclosure Number: IPCOM000109581D
Original Publication Date: 1992-Sep-01
Included in the Prior Art Database: 2005-Mar-24
Document File: 2 page(s) / 88K

Publishing Venue

IBM

Related People

Behnen, E: AUTHOR [+4]

Abstract

A shift register latch ML, SL with an additional small slave latch SL' is proposed which reduces the peak power of present VLSI chips by about 40%. Shift clock distribution is made much easier and the shift speed is increased. (Image Omitted)

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 55% of the total text.

Shift Register Latch for Peak Power Reduction

       A shift register latch ML, SL with an additional small
slave latch SL' is proposed which reduces the peak power of present
VLSI chips by about 40%.  Shift clock distribution is made much
easier and the shift speed is increased.

                            (Image Omitted)

      A standard shift register latch SRL (circuit part marked by
normal lines) consists of a master latch ML and a slave latch SL.
Data D0 is clocked into master latch ML with the master clock C0 and
into slave latch SL with the slave clock B0.  Slave output 30 is
connected to shift input I0 of the next SRL to form SRL chains.
Shift clock A0 allows loading master latch ML from the shift input.

      Present VLSI chips self-test such SRL chains.  The clock
sequence A0-B0 shifts a long random data pattern into the SRL chains.
The system clock sequence C0-B0 is active for one system cycle.
Subsequently, the results are again shifted.  The self-test creates
random patterns and increments some self-test registers.  A good chip
must have a definite register content at the end of the self-test.

      While the SRL chains are loaded, the random data propagates
through the logic without being used at the next master input.  This
leads to a high unnecessary power.  The power during the self-test is
about 5:3 higher than during normal use.  Thus, the self-test sets
maximum standards for power and cooling.

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