Browse Prior Art Database

Auxiliary Processor for Personal Computer Systems

IP.com Disclosure Number: IPCOM000109584D
Original Publication Date: 1992-Sep-01
Included in the Prior Art Database: 2005-Mar-24
Document File: 6 page(s) / 297K

Publishing Venue

IBM

Related People

Bealkowski, R: AUTHOR [+2]

Abstract

Described is an architectural implementation of an auxiliary processor (AP) for personal computer (PC) systems. The AP is designed to provide off-load processor capabilities so as to increase the overall performance of a PC system.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 39% of the total text.

Auxiliary Processor for Personal Computer Systems

       Described is an architectural implementation of an
auxiliary processor (AP) for personal computer (PC) systems.  The AP
is designed to provide off-load processor capabilities so as to
increase the overall performance of a PC system.

      Typically, PC systems utilize a single processor to perform all
system level activities.  This single processor is frequently
occupied with simple time-consuming input/output (I/O) operations.
Each instruction cycle used for the I/O operations can impact system
performance.  In addition, problems associated with the single
processor are generally limited self-test abilities of major
functional units and the complexity of supporting on-line
diagnostics.  As a result, the processor activities can have a
negative impact on the performance of an application.

      The concept described herein provides an AP that is dedicated
to I/O and diagnostic operations so that the central processor can
concentrate on the major system operations.  This, in-turn, will
increase the overall performance of an application.  Fig. 1 shows an
architectural block diagram of the functional units of a typical PC
system.  The I/O bus attaches to the various I/O feature devices.
These devices are the devices that would be controlled by the AP.
Since the AP would not execute user applications, there would be no
need to have a compatible instruction set for the AP.

      Fig. 2 shows an architectural block diagram of the AP
subsystem.  The AP operates from the existing system clock circuitry
and the local memory is small in relation to the main processor.  The
bus interface and the direct memory access (DMA) arbiter and control
logic are standard functional units.  The key element of the AP is
the interrupt interface.  Fig. 3 shows a block diagram of the
interrupt flow.  The AP can have access to all system interrupts,
similar to the main processor. There are four basic modes or types of
interrupt operation.  The four modes are described as follows:
      Mode 1 - Used to signal an interrupt from the AP to the main
processor.  This is required so as to provide communication between
the processors.
      Mode 2 - Used to allow the AP to obtain hardware interrupts.
This is required so as to allow the AP to manage the I/O devices.
      Mode 3 - Used as a pass-through mode to allow an interrupt to
pass transparently through the AP.  This is useful in situations
where the AP decides that the main processor is best suited to handle
a given interrupt.
      Mode 4 - Used as the existing mode of operation where
interrupts go directly to the main processor.

      Fig. 4 shows the architectural block diagram of the AP complex
imbedded into the personal computer system.  Typically, the AP is
attached to the channel or system bus so as to have access to all
system devices by way of a DMA interface.  The AP arbitrates for the
system...